June 15, 2026

Out of the shadows: Huawei’s ‘chip queen’ steps back into the spotlight with scaling law He Tingbo, Huawei’s semiconductor chief, reemerges to present the Tau Scaling Law, claiming transistor density gains without EUV lithography. The framework challenges Moore’s Law by prioritizing signal timing and introduces LogicFolding, sparking debate over its feasibility and impact. South China Morning Post

Sponsor DIE Stacking on a Small Area Assembly process where chips are stacked on top of one another on a substrate. This vertical integration allows a compact arrangement of different circuits with different dimensions on a small area. Tresky Automation

UCLA’s $125M Semiconductor Hub: “We Want High Impact, Not Incremental Research” UCLA Samueli partners with Broadcom, Applied Materials, GlobalFoundries, Meta, Synopsys to launch a $125 million semiconductor hub that drives AI chip innovation, uniting academia and industry to pursue high-risk research, reshape PhD training, and overcome compute, memory, and interconnect limits. EE Times

Eliminating Interfacial Delamination in High-Power Automotive Devices This study demonstrates that coating power devices with APTES adhesion promoter after wire bonding eliminates interfacial delamination, providing a simpler alternative to lead frame roughening technology. Technical Paper

Sponsor EZ-FLO High Precision Dispense Tips Each needle is machined from solid stainless steel as opposed to rolled tubing. The resulting smoother internal profile enhances material flow and consistency. Learn more. DL Technology

Infineon to open chip fabrication plant in Germany Infineon Technologies prepares to open its €5 billion Dresden semiconductor fab on July 2, backed by €1 billion EU subsidies. The plant boosts power chip output for AI data centers and supports Europe’s push for semiconductor self-reliance. Taipei Times

Minister defends TSMC amid US suit Taiwan’s economic affairs minister Kung Ming-hsin expresses confidence in TSMC’s patent compliance after US lawmakers urge a potential import ban over alleged infringement. An ITC judge expects a preliminary ruling this month, with a final decision due in October. Taipei Times

Sponsor How to Cold Bump Pull? Learn how to perform an optimal Cold Bump Pull test on solder balls using tweezers. This guide covers test method settings and failures modes for CBP all types of bump testing. xyztec

Technical Papers Automated X-Ray Metrology: Enhancing Quality and Efficiency in Wafer and Panel-Level Applications Alpha Particle Emissions: An Overlooked Risk for Soft Errors in Advanced Packaging Revolutionizing IC Packaging with High-Density RDL Technology EOTPR Fine pitch probing for die-to-die interconnect failure analysis in chiplet devices Die-on-Tab for Compound Semiconductors: Enabling Advanced RF Power Systems Package Assembly Design Kits: The Future of Advanced Package Design Novel Molded FCBGA Package Platform For Highly Reliable Automotive Applications MORE TECHNICAL PAPERS

Sponsor Fusion and Hybrid Bonding Experts EVG's industry-leading process solutions, expertise and HI Competence Center accelerate the development and implementation of heterogeneous integration technology. EV Group

Indian Firm Scales Single-Walled Carbon Nanotube Production for Batteries and Chips Carbon nanotubes are emerging for semiconductors, batteries, and water treatment as Bengaluru-based NoPo Nanotechnologies scales single-walled production. The startup builds a pilot plant and new facility, using HiPco process and tight control of 200 parameters to deliver uniform, application-ready materials. EE Times

Chip Industry Week In Review Cadence and Intel Foundry signed a multi-year deal to advance design co-optimization and develop PDKs for Intel’s 14A process. Nvidia and SK hynix partnered on AI memory. Teradyne and TEL introduced packaging test solution. VinRobotics and Infineon launched humanoid robotics collaboration. Semiconductor Engineering

Sponsor Die-on-Tab for Compound Semiconductors This white paper explains why die-on-tab is critical for GaN and GaAs RF power devices, improving heat dissipation, reliability, and system life. Download now. StratEdge Corporation

Ahead of SpaceX IPO, Elon Musk addresses ASML employees as part of push into chip manufacturing Elon Musk addressed ASML employees ahead of taking SpaceX public, highlighting the chipmaker’s role in his planned Texas Terafab plant. He praised ASML’s EUV technology, which enables advanced chip production essential for AI-focused ventures at Tesla, SpaceX, and xAI. CNBC

Quantum of promise: How to build a quantum chip Chip manufacturing and quantum computing converge complex physics and semiconductor engineering. Despite theoretical power, quantum computers rely on a single QPU using qubits in superposition. Industry remains small versus silicon, yet firms like IBM advance scalable superconducting quantum hardware. Data Centre Dynamics

Sponsor Advanced Packaging: Flexible Die Bonder Featuring a large, versatile working area, the MRSI-705 die bonder handles many input and output types, including 300mm wafers. MRSI

RISC-V Targets Data Centers, Edge AI, Space RISC-V now targets data centers, edge AI, and space missions as industry standardization and RVA23 server specs accelerate commercial adoption, with major chip launches, rising investment, and growing software support positioning it as a scalable alternative to ARM and x86. EE Times

To beat chip crunch, Chinese firm inks memory deal bigger than its sales Biwin signed a $1.86 billion two-year agreement to secure flash memory chips, exceeding its annual revenue. The company locks in supply from 2026 to 2028 as AI-driven data centre demand tightens global memory markets and drives prices higher. South China Morning Post

Sponsor AIT ORMET® TLPS for Proven Reliability AIT ORMET® TLPS is proven for outstanding reliability for High and Ultra High-Density Interconnection and high temperature build-up Layer Interconnection beyond 175°C Ormet® TLPS

Imec unlocks system-level III-V chiplet integration Imec advances a 300mm RF silicon interposer platform integrating III-V chiplets with Si-CMOS, enabling mmWave and sub-THz systems. It adds high-density embedded capacitors, scalable passive modeling, and laser-assisted bonding, improving performance, integration efficiency, and manufacturability for wireless and data-centre applications. Compound Semiconductor

Sponsor Rapid Package Seam Seal Changeover The Robotic Cover Sealer (RCS) enables rapid assembly changeover on < 5 minutes from a 3 x 3 mm to 50 x 70 mm package. Package tooling may be adjustable or tool less. MicroCircuit Laboratories, LLC