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May 29, 2026 Chiplets, Ecosystems, and Europe's Post-Fab Semiconductor Strategy Europe is shifting its semiconductor strategy from building fabs to strengthening the full chip ecosystem. Industry leaders back Chips Act 2.0, chiplets, and heterogeneous integration to boost design, interoperability, and system-level innovation. EE Times May 29, 2026 This is the greatest time ever for semiconductors, says CEO of key equipment supplier Applied Materials CEO Gary Dickerson said the semiconductor industry is entering its strongest era driven by surging AI demand, with sustained growth visibility into 2027–28, expanded capacity investments and continued momentum in advanced chip manufacturing equipment. CNBC May 29, 2026 Focused light raises 2D semiconductor current up to 63-fold Researchers at DGIST developed a laser-assisted microlens method to precisely tune defects in MoS₂, boosting transistor on-current up to 63 times and mobility 51 times, enabling low-damage, atomic-level doping for next-generation 2D semiconductor chips applications. Nanowerk May 29, 2026 AI in Design Verification: From Experimentation to Measurable Capability AI in design verification is shifting from concept to real-world deployment, helping engineers with regression triage, debug, coverage analysis, and log summarization. Teams now measure success through risk reduction, traceability, and stronger verification efficiency. EE Times May 29, 2026 Finding Success in Industry as a Chip Designer An ASIC designer describes the shift from academia to industry, where silicon IP dominates chip development. He highlights how risk-averse economics, strict schedules, system integration, and rigorous verification now drive modern semiconductor design. IEEE Spectrum May 29, 2026 Swapping Out Chiplets: I/Os Vs. Compute Chiplet architectures enable modular chip design by letting engineers reuse core compute while selectively swapping I/O, memory, or protocol blocks. Driven by AI and HPC demands, this approach reduces costly respins and aligns performance with rapidly evolving standards. Semiconductor Engineering May 29, 2026 Toward Agentic Verification Agentic verification is reshaping semiconductor design by using AI agents to automate verification flows, generate tests, debug failures & accelerate coverage closure. Engineers still must control costs, address analog limitations, manage context gaps & maintain human oversight. Semiconductor Engineering May 29, 2026 Observability Is Essential For Modern Silicon In-silicon observability is gaining importance for managing performance, reliability & security in advanced chips. Experts from Arteris, Baya Systems, Cadence, Keysight EDA, Movellus, Siemens EDA, Synopsys & Vinci discuss how on-die visibility improves debugging & system optimization. Semiconductor Engineering May 29, 2026 Using SystemC TLM Modeling To Solve AI Data Movement Challenges AI chip performance depends on efficient data movement, not just compute metrics. Engineers use SystemC TLM modeling to simulate NoC behavior early, identify bottlenecks, and refine architectures through iterative feedback, improving bandwidth, latency, and reducing design risk. Semiconductor Engineering May 29, 2026 Faster Verification Debug With AI Agentic verification is transforming chip design as AI agents automate test generation, debug failures, orchestrate verification flows, and speed coverage closure. Engineers still must manage costs, analog gaps, context limits, and human oversight in practice. Semiconductor Engineering |
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