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Jan 14, 2026 Wafer Probe Struggles To Adapt To Multi-Die Assemblies Wafer probe, once a routine semiconductor screening step, is now a critical yield risk in AI-class, multi-die devices. Rising I/O counts, larger chip sizes, and advanced packaging amplify mechanical stress, making electrical pass/fail data insufficient for ensuring device reliability. Semiconductor Engineering Jan 14, 2026 VIEWPOINT 2026: Nitin Parekh, CEO, Via Automation In today's semiconductor industrial landscape, downtime is more costly than ever. Unplanned machine downtime cost manufacturers more than $1.5 trillion globally per year. The cost of a single hour of downtime has surged by 50% in just two years. Similarly, semiconductor manufacturing is inefficient ... Via Automation Jan 14, 2026 Arizona fabs could meet US' chip demand: economist TSMC may expand its Arizona operations to six–eight fabs, producing 150,000 wafers monthly, nearly covering US demand for AI and high-performance chips. The move, part of a tariff deal, could create a dual-hub model while raising costs and geopolitical stakes. Taipei Times Jan 14, 2026 Prices of 8-inch wafers to rise 20 percent Chipmakers are set to raise 8-inch wafer prices by up to 20% this year as TSMC and Samsung retire older capacity, tightening supply. Rising AI and consumer electronics demand is driving higher fab utilization and early orders from PC makers. Taipei Times Jan 14, 2026 Chip demand fuels recovery in machine exports Taiwan's machinery industry rebounded strongly in 2025, with exports rising 9.1% to US$31.86 billion. Growth was driven by electronic and testing equipment, while machine tool exports fell, challenged by weak demand, currency strength, and global competition. Taipei Times Jan 14, 2026 India aims to be among the major semiconductor hubs by 2032, says Union Minister Ashwini Vaishnaw India is accelerating its domestic semiconductor push, with 10 approved units and four plants set to start production in 2026. Backed by AI, EV, and electronics demand, the government is expanding design, talent, and manufacturing to become a global chip hub by 2032. ELE Times Jan 14, 2026 A Clear Advantage: Precision Glass Carrier Inspection For AI And HPC Markets Advanced packaging is turning to glass carriers to enable HBM, chiplets, and 3D integration, prized for flatness, rigidity, and optical alignment. AI-powered inspection spots surface, subsurface, and stress defects, lifting yields and reliability. Semiconductor Engineering Jan 14, 2026 Semiconductor Manufacturing In The AI Era At the 2025 PDF Solutions Users Conference, CEO John Kibarian said AI is driving growth as chip complexity soars. He urged collaboration, data use and AI automation to hit $1T revenue by 2030 amid 3D packaging, supply chain splits and talent gaps. Semiconductor Engineering Jan 14, 2026 Secure Data Sharing Becoming Critical For Chip Manufacturing Semiconductor companies are sharing data to lift yields and trace failures. Secure, anonymized data powers predictive analytics and early fault detection, helping fabs, fabless firms and data centers speed production while protecting IP worldwide. Semiconductor Engineering Jan 14, 2026 HBM4 Sticks With Microbumps, Postponing Hybrid Bonding JEDEC's revised HBM4 standard allows 16-high memory stacks without hybrid bonding, delaying but not canceling adoption. HBM4 boosts AI with wider, faster interfaces and better efficiency, while hybrid bonding enables future taller, thinner stacks. Semiconductor Engineering |
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