July 3, 2026

Engineering Heterogeneity at Scale AI is reshaping semiconductor design by shifting the focus from transistor scaling to system-level integration. Imec says advances in 3D stacking and heterogeneous large-scale integration enable designers to combine specialized technologies, improving compute performance by optimizing data, power, and heat across complex chip packages. EE Times

Sponsor Ultra-Thin Wafer Handling Brewer Science temporary wafer bonding systems allow for safe handling and transport of ultrathin wafers during rigorous backside processing steps. Brewer Science

Machvision touts positive outlook as AI demand holds Machvision expects strong order growth through the first half of next year as AI-driven chip demand fuels inspection tool purchases. The company raised prices, expanded its backlog, secured major customer orders, and expects shipments of optical transceiver modules to begin this quarter. Taipei Times

Eliminating Interfacial Delamination in High-Power Automotive Devices This study demonstrates that coating power devices with APTES adhesion promoter after wire bonding eliminates interfacial delamination, providing a simpler alternative to lead frame roughening technology. Technical Paper

Sponsor 1 of 10 Applications: Flip-Chip Flip chip bonding at an accuracy of 5 µm or better is simple with Swiss made Tresky die bonders, at temperatures of up to 400°C, both in manual and in semiautomatic mode. Dr. Tresky AG

Global notebook exports to fall amid rising prices: expert TrendForce forecasts global notebook shipments to fall 13.6% this year as higher component costs drive price increases and weaken consumer demand. While business and education sales remain stable, rising prices could curb replacement cycles, with Apple expected to outperform rivals despite slower MacBook growth. Taipei Times

Rapid Component Obsolescence Is Reshaping Today’s Semiconductor Procurement Dynamics Semiconductor obsolescence now poses a persistent supply chain risk, pushing procurement teams to adopt proactive lifecycle management, diversify sourcing, strengthen inventory planning, and collaborate with engineering to maintain production, reduce redesign costs, and ensure long-term component availability amid rising market pressures. EE Times

Sponsor Nordson Sight™ Nordson Sight™ delivers scalable SPC with traceability, rapid setup, intuitive interface, and powerful analysis tools for improved manufacturing yields. Nordson Test & inspection

Technical Papers Automated X-Ray Metrology: Enhancing Quality and Efficiency in Wafer and Panel-Level Applications Alpha Particle Emissions: An Overlooked Risk for Soft Errors in Advanced Packaging Revolutionizing IC Packaging with High-Density RDL Technology EOTPR Fine pitch probing for die-to-die interconnect failure analysis in chiplet devices Die-on-Tab for Compound Semiconductors: Enabling Advanced RF Power Systems Package Assembly Design Kits: The Future of Advanced Package Design Novel Molded FCBGA Package Platform For Highly Reliable Automotive Applications MORE TECHNICAL PAPERS

Sponsor Die-to-Wafer Bonding Simplified Researchers developed a plasma Die-to-Wafer bonding process, eliminating complex carrier wafers & costly vacuum systems, enhancing 3DIC & integrated photonics applications. Ontos Equipment Systems

Sales Forecasting Guide for Electronics Manufacturing SMBs Sales forecasting enables electronics manufacturers to anticipate demand, align production, procurement, and inventory, and manage long component lead times. Accurate forecasts reduce stockouts, production delays, and excess inventory while improving planning, cash flow, and responsiveness to changing customer requirements. EE Times

The Rise of Fabless Chip Design Companies in India: Driving Global Innovation and Indigenous Silicon Autonomy India’s fabless chip design companies are driving a major shift in the global semiconductor industry, evolving from engineering support hubs into deep-tech IP creators. Leveraging the country’s mature talent pool, they are developing specialised, globally competitive integrated circuits for international markets. BIS Infotech

Sponsor Epoxy & Adhesive DIE Bonding One of the most common methods of creating a connection between chip and substrate is the gluing process. Extreme precise epoxy & adhesive bonding processes for sustainable bonds. Tresky Automation

EU Chips Act 2: Award-Winning Sequel or Straight to Video? The proposed EU Chips Act 2.0 expands beyond manufacturing to strengthen semiconductor resilience through chip design, multi-foundry flexibility, and lab-to-fab transitions. By prioritizing design-layer capabilities alongside fabs, the EU aims to build a more adaptable and secure semiconductor ecosystem. EE Times

Taiwan silicon wafer suppliers signal further price hikes Taiwan's leading silicon wafer suppliers are preparing further price hikes in the second half as AI-driven demand, stronger utilization rates and shrinking legacy wafer capacity tighten supply. Recovering mature-chip markets and ongoing pricing talks are expected to sustain semiconductor supply chain momentum. Taiwan News

Sponsor AIT ORMET® TLPS for Thermal Conductivity AIT ORMET® TLPS is proven with stress relief for stable long-term metallic thermal conductivity & low thermal interface resistance for high temp >175°C Ormet TLPS

Securing the Software Defined Vehicle: How Rambus and Telechips Enable Safe, Scalable Automotive SoC Automakers are accelerating the shift to centralized zonal architectures for software-defined vehicles, consolidating AI, ADAS, cockpit, and OTA functions onto high-performance SoCs. To strengthen security, Telechips is developing scalable SoCs with hardware-based Root of Trust for secure boot, key management, and trusted operation. Semiconductor Engineering

Observability Is A Missing Layer In AI-Era Chiplet Design Chip industry experts say in-silicon observability is becoming essential for improving performance, reliability and security in advanced semiconductor systems. They highlight growing demand for on-chip data analytics and resilience as chip complexity, AI workloads and system integration continue to increase. Semiconductor Engineering

Sponsor EZ-FLO High Precision Dispense Tips Each needle is machined from solid stainless steel as opposed to rolled tubing. The resulting smoother internal profile enhances material flow and consistency. Learn more. DL Technology

ASE Reportedly Raises Advanced Packaging Quotes by 20% in Latest AI-Driven Price Hike ASE has reportedly increased advanced packaging prices by more than 20% as AI demand, rising raw material costs, and heavy capital investments tighten capacity. The latest increases affect key technologies such as CoWoS and FoCoS, raising costs for major chip customers. TrendForce

Sponsor Copper Stud & CTE Nano Tech Underfill AIT's proven flip-chip and BGA multi-level underfills offer both 18 ppm/°C copper CTE matching fine-pitch & nano-pitch with 10 µm & 0.3 µm respective cut-off particles. AI Technology, Inc.