Aug 26, 2026 Gartner Forecasts Worldwide Semiconductor Revenue to Reach $1.6 Trillion in 2026 AI infrastructure is pushing global semiconductor revenue toward $1.6 trillion in 2026, nearly doubling 2025 levels. Memory leads growth as DRAM and NAND demand accelerates, while investment expands in CPUs, networking, power and optical tech. Gartner

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Intel Unveils Three AI Architectures at Hot Chips 2026, Diamond Rapids Taps In-House 18A-P and Packaging Intel unveiled AI-focused architectures at Hot Chips 2026: Diamond Rapids for agentic AI, Crescent Island for inference, and Wildcat Lake for edge devices. Diamond Rapids pairs 256 cores with 1.28GB cache and 16 memory channels for data centers. TrendForce

How AI Could Cut Semiconductor Package Design Cycles from Months to Days This paper explores how AI-powered semiconductor package design tools can accelerate development, reduce errors, optimize performance and sustainability, and enhance engineer productivity, transforming package design cycles from months to days. Technical Paper

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Welcome to the Era of Trustworthy AI for IC Signoff and Manufacturing Trustworthy AI could transform chip design and manufacturing, but engineers must retain control. Combining explainable AI with deterministic EDA engines can speed verification, improve yield and cut costly respins without sacrificing reliability. EE Times

China Flash Unveils 28nm NOR Flash with 2Gb Capacity, Reportedly Reaching Industry's Most Advanced Node China Flash has unveiled 28nm second-generation NOR Flash, claiming the first sub-40nm NOR process and 2Gb single-die capacity. Its proprietary architecture boosts efficiency and cuts power, but yield and mass production remain key hurdles. TrendForce

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Technical Papers ■ How AI Could Cut Semiconductor Package Design Cycles from Months to Days ■ 5X Faster Die Sorting Accelerates U.S. Semiconductor Manufacturing ■ A New Optical Ball Grid Array Package Development for Automotive Optical Sensor ■ Automated X-Ray Metrology: Enhancing Quality and Efficiency in Wafer and Panel-Level Applications ■ Alpha Particle Emissions: An Overlooked Risk for Soft Errors in Advanced Packaging ■ Revolutionizing IC Packaging with High-Density RDL Technology ■ EOTPR Fine pitch probing for die-to-die interconnect failure analysis in chiplet devices MORE TECHNICAL PAPERS

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Indian firm orders 9,000 of Nvidia's AI systems India's AM Intelligence ordered 9,000 Nvidia Vera Rubin systems for AI data centers, with servers due online in 2027. The $8 billion plan targets 1GW of capacity, powered by low-cost renewables, for global AI customers and Indian model development. Taipei Times

SEMI and THSRC collaborate for Semicon Taiwan SEMICON Taiwan partners with Taiwan High Speed Rail to offer event check-in at five stations and boost capacity. The link connects semiconductor hubs, eases congestion and helps more than 100,000 global attendees visit suppliers efficiently. Taipei Times

Sponsor New PLP solution improves underfill yields Underfill yields were greater than 99% and cycle time decreased 30% with the ASYMTEK Vantage system for panel-level packaging (PLP). Learn more. Nordson Electronics Solutions

Why is Xiaomi doubling down on in-house chips amid a profit slump? Xiaomi is advancing its proprietary silicon strategy with 3nm Xring O3 and new AI and autonomous-driving chips, targeting smartphones and cars. The push strengthens its China chip position as rising component costs pressure profits. South China Morning Post

Redefining Roles For Edge And Cloud AI Edge AI is shifting intelligence from the cloud to devices, using smaller, targeted models for faster responses and greater privacy. Co-optimized edge-cloud systems will expand rapidly, with 100 billion models already running locally today. Semiconductor Engineering

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Research Bits: Aug. 25 MIT researchers built bacterial transistors for environmental sensing, while South Korean scientists created a device that forgets old inputs for time-series AI. Carnegie Mellon and Penn State researchers turned an oxide into a semiconductor. Semiconductor Engineering

NXP Expands Industrial Endpoint Access with MCU Topology Discovery NXP's MCX A5 MCUs bring IP connectivity to industrial endpoints through 10BASE-T1S Ethernet and automated topology discovery. PQC security, secure boot and attestation protect nodes, while visibility supports diagnostics, automation and edge AI. EE Times

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Nvidia says Groq racks will be online this year following $20 billion purchase Nvidia puts its Groq 3 LPX rack into full production, targeting low-latency AI inference alongside Vera Rubin systems. The rack packs 256 Groq chips and delivers 3,400 tokens per second, giving cloud providers premium, responsive service options. CNBC

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Multi-Die Assemblies Dominate At 2nm And Below AI workloads are pushing chip design beyond monolithic dies, accelerating chiplets and heterogeneous integration. Engineers are advancing packaging, interposers, materials, memory and edge-AI architectures to deliver higher performance per watt. Semiconductor Engineering