Sep 2, 2026 The imec Report: Advancing The CFET-Based Device Roadmap imec is advancing CFET technology to extend semiconductor scaling into the angström era. Its improved backside-contacting module delivers fivefold higher bottom pFET drive current and raises survival yield from 45% to 85%, strengthening prospects for industrial adoption. Semiconductor Engineering

Sponsor 1 of 10 Applications: Sinter Sintering high-power semiconductors with silver or copper interfaces is easy with Swiss made Tresky die bonders at temperatures over 300°C and low or high bond forces. Dr. Tresky AG

Intel CFO Says 14A Defect Reduction Fastest Since 22nm; Customer Talks Reportedly Grow Ahead of 2028 Ramp Intel says 14A defect density is improving faster than expected, signaling strong process learning despite greater complexity. Rising customer interest, a 2027 risk-production target and 2028 ramp could put Intel on par with TSMC's A14 timeline. TrendForce

Revolutionizing IC Packaging with High-Density RDL Technology Amkor's S-SWIFT packaging technology addresses advanced IC packaging challenges through an embedded trace RDL process, providing higher bandwidth die-to-die interconnects for AI, HPC, and data center applications with improved reliability. Technical Paper

Sponsor Buy Ceramic Dispensing Needles Online Ceramic needles with Luer Lok for conductive epoxies and encapsulation. The ceramic molding process allows for smaller more precise inner diameters with a glass like finish. Buy Online. DL Technology

Here Comes the Sun: Why the Co-Packaged Optics Transition Is "All Right" Co-Packaged Optics (CPO) is gaining momentum as AI drives demand for faster, more energy-efficient data movement. By bringing optical links closer to processors and switches, CPO reduces electrical signal distances and improves high-speed networking efficiency. 3DIncites

IEEE President's Note: Technology for Social Good IEEE's Humanitarian Technologies programs bring engineers together to address global challenges through responsible innovation. The initiatives expand IEEE's societal impact, engage younger professionals, build leadership skills, and strengthen its role in purpose-driven engineering. IEEE Spectrum

Sponsor High power atmospheric plasma system Our 1000 Atmospheric Plasma System is available with PC or PLC control for lab or high speed production use with the same high powered systems. Remove contaminants and increase bond strength! Plasma Etch

Technical Papers ■ How AI Could Cut Semiconductor Package Design Cycles from Months to Days ■ 5X Faster Die Sorting Accelerates U.S. Semiconductor Manufacturing ■ A New Optical Ball Grid Array Package Development for Automotive Optical Sensor ■ Automated X-Ray Metrology: Enhancing Quality and Efficiency in Wafer and Panel-Level Applications ■ Alpha Particle Emissions: An Overlooked Risk for Soft Errors in Advanced Packaging ■ Revolutionizing IC Packaging with High-Density RDL Technology ■ EOTPR Fine pitch probing for die-to-die interconnect failure analysis in chiplet devices MORE TECHNICAL PAPERS

Sponsor No more cartridge exchanges The unique Revolving Measurement Unit (RMU) houses up to 6 sensors of any type that enable continuous pull/push and shear testing up to 200 kgf. Learn more. xyztec

GlobalWafers acclaims new tech GlobalWafers expects advanced packaging wafers to contribute significantly to revenue this year as production ramps up. The company sees strong AI-driven semiconductor demand, rising wafer prices, high utilization, and growing long-term customer commitments. Taipei Times

How AI Is Reshaping the Global Semiconductor Patent Landscape AI workloads are driving a surge in semiconductor patenting as chipmakers target custom silicon, advanced memory and new architectures. AI-semiconductor filings rose 114% in five years, with Samsung leading architecture patents while Intel and Qualcomm expand aggressively. EE Times

Sponsor IR Layer Release Technology for 3D Packaging and Logic Scaling Ultra-thin layer transfer from silicon carriers with nanometer precision using an IR laser and inorganic release layers revolutionizes 3D packaging & logic scaling. EV Group

As Chinese chipmakers snap up local gear, self-sufficiency drive faces commercial test Chinese chipmakers are rapidly increasing local equipment targets, pushing domestic toolmakers to prove commercial reliability. Rising demand is boosting Chinese suppliers, while semiconductor equipment localisation is projected to reach 39% by 2030 as fab investment expands. South China Morning Post

ASML Advances High-NA EUV Toward HVM as 10 Systems Reportedly Go Live at 4 Customers ASML says High-NA EUV is nearing broad HVM adoption, with 10 systems running at four customers. Intel already uses it for 18A Panther Lake chips, while ASML targets 210+ WPH and sees the technology scaling future DRAM nodes and cutting costs. TrendForce

Sponsor Copper Stud & CTE Nano Tech Underfill AIT's proven flip-chip and BGA multi-level underfills offer both 18 ppm/°C copper CTE matching fine-pitch & nano-pitch with 10 µm & 0.3 µm respective cut-off particles. AI Technology, Inc.

SK Hynix's $4B HBM Project Targets U.S. Chipmaking Gap SK Hynix will invest $4 billion in Indiana to package and test HBM chips by 2029, strengthening U.S. semiconductor supply chains. The facility will produce HBM4E, support advanced packaging R&D, and foster a local ecosystem with Purdue University and suppliers. EE Times

Taiwan's chips link global partners, strengthen supply chain: President Taiwan President Lai Ching-te said semiconductors strengthen global ties, diversify supply chains and boost resilience. He cited Nvidia, Micron, AMD and TSMC investments and pledged support for advanced technology, infrastructure and partnerships. Focus Taiwan

Sponsor Advanced Packaging and Electronic Assembly Cleaning Fluid Innovation This paper will present aqueous cleaning technology innovations to address the challenges of cleaning highly dense electronic hardware. Read more. KYZEN

Research Bits: Sept. 1 Researchers developed advanced GaN technologies that withstand nearly 4 kV, reduce contact resistance, and improve thermal management. The innovations could boost efficiency, reliability, and performance in EVs, industrial systems, wireless communications, radars, and data centers. Semiconductor Engineering

Sponsor Ultrasonic Bonding: Cohesive connection between a chip & substrate Electrically conductive and mechanical bonds for temp-sensitive components or components that are difficult to heat with Ultrasonic Bonding. Tresky Automation

Global chip market to exceed US$2tn by 2030: SEMI The global semiconductor market could exceed US$2 trillion by 2030, driven by AI infrastructure demand for advanced chips, HBM, DRAM, NAND, testing and packaging. SEMI also raised forecasts for wafer equipment, materials and Taiwan's semiconductor contribution. Taipei Times