April 10, 2026

Intel in Talks with Google and Amazon to Power AI Chips with New Packaging Tech Intel is betting advanced chip packaging will drive its comeback, holding talks with Google and Amazon to win AI silicon business from TSMC. With new tech like EMIB-T and major investments, Intel aims to turn packaging into a billion-dollar revenue engine. TechSpot

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AI Chip Supply Chain Faces Packaging Bottleneck Advanced chip packaging is becoming a major bottleneck in the AI supply chain as demand surges and capacity remains concentrated in Asia. U.S. firms still ship chips to Taiwan, while Intel pushes domestic packaging to capture growing market opportunities. National Today

Revolutionizing IC Packaging with High-Density RDL Technology Amkor's S-SWIFT packaging technology addresses advanced IC packaging challenges through an embedded trace RDL process, providing higher bandwidth die-to-die interconnects for AI, HPC, and data center applications with improved reliability. Technical Paper

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TSMC's Chipmaking Edge Is So Strong That Competitors Are Fighting to Work with Its Supply Chain Partners, Viewing Them as a Winning Bet TSMC strengthens semiconductor dominance by enforcing strict supplier standards that rivals Intel, Rapidus, and Elon Musk's TeraFab seek to emulate by sourcing Taiwanese partners, leveraging validated supply chains, while Taiwan remains a critical global chip ecosystem hub. wccftech

Intel Enters Pact With Tesla and SpaceX for Terafab Intel partners with Elon Musk’s Tesla, SpaceX, and xAI to build Terafab in Texas, aiming to design and manufacture ultra-high-performance AI chips. The venture leverages Intel’s 18A process and packaging to challenge TSMC and Samsung supply constraints. EE Times

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Technical Papers Alpha Particle Emissions: An Overlooked Risk for Soft Errors in Advanced Packaging Revolutionizing IC Packaging with High-Density RDL Technology EOTPR Fine pitch probing for die-to-die interconnect failure analysis in chiplet devices Die-on-Tab for Compound Semiconductors: Enabling Advanced RF Power Systems Package Assembly Design Kits: The Future of Advanced Package Design Novel Molded FCBGA Package Platform For Highly Reliable Automotive Applications Eliminating Interfacial Delamination in High-Power Automotive Devices MORE TECHNICAL PAPERS

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Google expands partnership with Intel for AI chips Google expands its partnership with Intel, deploying multiple generations of Xeon 6 CPUs in AI data centers for training and inference workloads. The move strengthens Intel's position against Nvidia, while both companies also advance infrastructure processing unit collaboration. CNBC

Chip Can Project Video the Size of a Grain of Sand Researchers in the MITRE Quantum Moonshot project developed a 1mm² photonic chip that steers tens of millions of light spots per second, potentially enabling scalable control of millions of qubits while also advancing augmented reality, imaging, and 3D scanning applications. IEEE Spectrum

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Which Chips Actually Matter? Europe Reassesses Its Semiconductor Strategy After Nexperia Wakeup Call Europe is pivoting its semiconductor strategy from chasing leading-edge nodes to securing critical chips for autos, sensors, security, and packaging. Policymakers now prioritize resilient value chains, trusted niches, and industrial strengths over prestige fabs and full self-sufficiency. EE Times

The Coming Breakup Between AI And The Cloud Cloud AI is giving way to edge intelligence as devices run models locally. Packet-based NPU designs improve efficiency, raising utilization from 20–40% to 60–80%, cutting memory use and power, and enabling major performance gains in real-world deployments. Semiconductor Engineering

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Power Integrity Without Blind Spots: A System Level Approach To 3D-ICs Power delivery challenges intensify in 2.5D and 3D IC designs as stacked architectures amplify noise and IR drop. Siemens’ Innovator3D IC unifies system-level power integrity analysis, integrating dies, interposers, and packages to detect risks earlier and improve signoff confidence. Semiconductor Engineering

DRAM's Whac‑A‑Mole Security Crisis Rowhammer and Rowpress continue to threaten DRAM as scaling reduces margins. Mitigations like TRR, RFM, ARFM, and DRFM are only partly effective and bypassable. Industry seeks better refresh control, transparency, and new vertical-cell DRAM designs for a lasting fix. Semiconductor Engineering

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A New Era For Co-Processing AI workloads drive rapid evolution of heterogeneous processors, but no single design fits all. CPUs, GPUs, DSPs, and NPUs specialize for tasks, yet data movement and integration challenges force architects to balance programmability, efficiency, and system-level co-design. Semiconductor Engineering

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