June 26, 2026

Chip tech to deliver major performance leap: IBM IBM unveiled a 0.7-nanometer chip technology that could boost performance by up to 50% or improve energy efficiency by 70%. Using a new 3D “nanostack” architecture, the breakthrough targets AI-driven computing, with commercial production expected within five years. Taipei Times

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Records Fall for 3D Chip Tech Researchers achieved record-breaking hybrid bonding advances for 3D chip stacking, dramatically increasing chip-to-chip connection density and improving power efficiency. The breakthroughs move next-generation AI and high-performance computing closer to reality, though manufacturing yields and large-scale production remain significant challenges. IEEE Spectrum

Current Characterization of Various Cu RDL Designs In Wafer Level Packages (WLP) This study evaluates copper redistribution layer fusing currents in wafer-level packaging through experiments and simulations, finding that silicon thickness significantly improves heat dissipation and fusing performance. Technical Paper

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Wafer-Scale vs. Chiplets: The New War? Part 2 Cerebras’ wafer-scale architecture and CoWoS-based chiplet designs tackle AI data movement bottlenecks through different approaches, but both highlight that efficient interconnects, memory hierarchy, bandwidth, and energy optimization must be integrated early in system design to maximize performance and scalability. Semiconductor Engineering

ON Semiconductor strikes $7 billion deal for Synaptics in physical AI push ON Semiconductor will acquire Synaptics in a nearly $7 billion all-stock deal to expand its physical AI capabilities, adding connected computing, software and intelligent systems expertise. The acquisition significantly enlarges its addressable market and is expected to close by mid-2027. CNBC

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Technical Papers Automated X-Ray Metrology: Enhancing Quality and Efficiency in Wafer and Panel-Level Applications Alpha Particle Emissions: An Overlooked Risk for Soft Errors in Advanced Packaging Revolutionizing IC Packaging with High-Density RDL Technology EOTPR Fine pitch probing for die-to-die interconnect failure analysis in chiplet devices Die-on-Tab for Compound Semiconductors: Enabling Advanced RF Power Systems Package Assembly Design Kits: The Future of Advanced Package Design Novel Molded FCBGA Package Platform For Highly Reliable Automotive Applications MORE TECHNICAL PAPERS

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Realizing The Future Of 3D-IC Design Heterogeneous chiplet technology is reshaping semiconductor design by enabling scalable, cost-effective system-in-package architectures. To fully realize its performance, power, and flexibility benefits, the industry must adopt system-centric design tools and workflows tailored for advanced 2.5D and 3D integrated circuits. Semiconductor Engineering

Executive Outlook: Agentic AI’s Impact On Chip Design Industry leaders examined how agentic AI is reshaping chip design and verification, highlighting its potential to accelerate development, improve productivity, and streamline workflows while addressing concerns over reliability, trust, human oversight, and integration into existing semiconductor engineering processes. Semiconductor Engineering

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Future Transistor Stacking Plans Start to Diverge IBM and leading chipmakers are advancing complementary field-effect transistor (CFET) technology, but diverge on manufacturing approaches. IBM’s sequential Nanostack design promises major gains in performance, efficiency, and chip density, while commercial adoption remains about six years away. IEEE Spectrum

IBM Shows Sub-1-nm Chips, Targeting Production in 5 Years IBM unveiled the world’s first 0.7-nm chip technology, introducing its 3D Nanostack architecture to double transistor density and significantly improve SRAM scaling. The company aims for partner production within five years, targeting faster, more efficient AI processors beyond the 1-nm era. EE Times

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Reducing Avoidable Memory Trips In HBM Systems High-bandwidth memory boosts AI system throughput but cannot eliminate latency caused by repeated external memory access. A last-level cache improves performance by keeping reusable data on chip, reducing memory trips, lowering idle cycles, and enabling faster, more efficient data sharing across compute engines. Semiconductor Engineering

Qualcomm Forecasts Billions in Additional Revenue from New Data Center Solutions Qualcomm has rapidly advanced its AI data center strategy through key acquisitions, hyperscale customer wins, and a new product roadmap. The company aims to deliver rack-scale CPU, AI, and networking solutions, positioning its data center business to surpass $1 billion in annual revenue. EE Times

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Verification Methodologies Struggle To Keep Up With AI AI is rapidly reshaping EDA workflows as chip companies race to accelerate verification, boost engineering productivity, and shorten time to market. While AI agents help senior and junior engineers alike, the industry still lacks proven methodologies for ensuring consistent quality and reliable deployment. Semiconductor Engineering

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