April 25, 2025

TSMC Announces World-Leading A14 Node to Power AI TSMC unveiled its A14 chip process, promising 15% speed boosts or 30% power cuts over N2, plus 20% higher logic density. Set for 2028 AI deployments, A14 integrates silicon photonics and aims to cut data center energy consumption. EE Times

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Tape-Out Failures Are The Tip Of The Iceberg The latest Wilson Research/Siemens survey exposes a steep fall in manufacturable chip designs—from 24% to 14%—and growing delays, as AI pressure, lagging EDA productivity, and inflated expectations fuel systemic inefficiency and industry-wide recklessness. Semiconductor Engineering

Electromigration Performance Of Fine-Line Cu RDL For HDFO Packaging The study highlights High-Density Fan-Out (HDFO) packages' fine copper redistribution layer (Cu RDL) reliability under electromigration (EM). Findings include distinct failure modes, resistance changes, and current-carrying capacity estimations crucial for advanced electronics design. Technical Paper

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Intel AI Trick Spots Hidden Flaws in Data-Center Chips Intel engineers are using reinforcement learning to boost detection of silent data errors in Xeon chips, which often evade traditional tests in hyperscale data centers. Their method improves detection fivefold by optimizing matrix-based Eigen test selection. IEEE Spectrum

SK Hynix warns of increased volatility in second half of year from US tariffs SK Hynix posted a 158% jump in Q1 operating income, driven by AI chip demand and stockpiling ahead of U.S. tariffs. Despite market volatility, it reaffirmed strong HBM growth, ongoing Nvidia collaboration, and a major DRAM plant expansion. Taipei Times

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Technical Papers A study about 3D stacking of passive SMD elements for advanced SMT packaging using laser assisted bonding Optimizing Cleaning Strategies for Advanced Packaging Technologies with Low Standoff Components In situ hydrogen plasmas — A New Paradigm for Advanced Packaging Multi-Sensor Metrology for the most challenging Advanced Packaging Applications Effect of Package Warpage and Composite CTE on Failure Modes in Board-Level Thermal Cycling Package Integrated Vapor Chamber Heat Spreaders Ultrasonic Bonding in semiconductor industry – The fast and clean process MORE TECHNICAL PAPERS

Sponsor Cleaning Silicone and Hydrocarbon Residue Using Atmospheric Plasma Residue from dicing tape and silicone trays can hinder chip bonding. ONTOS effectively cleans surfaces before bonding. Read more. Ontos

TSMC's cutting-edge A14 tech to hit fabs in 2028 TSMC unveiled its A14 chip process, set for 2028 production, promising faster AI computing and improved power efficiency. The company also announced an A16 intermediary process for 2025, underscoring its push to lead in next-gen semiconductor innovation. Taipei Times

Data Movement Is the Energy Bottleneck of Today's SoCs As AI accelerates SoC complexity, efficient data movement now rivals compute power in importance. Packet-based network-on-chip (NoC) architectures lead the way, enabling low-latency communication, cache coherence & chiplet integration across modular, high-performance semiconductor designs. Semiconductor Engineering

Sponsor High-volume Manufacturing The STA-10iL automated plasma system enhances substrate bonding. It features in-line conveyance for high-speed production, with an optional drawer for flexible, high mix operations. Surfx Technologies

AI-Driven Verification Regression Management Synopsys VC ExecMan is revolutionizing chip verification by integrating AI, machine learning, and advanced regression automation to streamline planning, execution, analysis, and debugging—boosting efficiency, coverage, and quality while slashing time to tape-out. Semiconductor Engineering

Asia/Pacific AI Spending to Reach $175 Billion by 2028, Driven by GenAI Boom, Says IDC AI and generative AI spending in Asia/Pacific is surging, expected to hit $175 billion by 2028. Driven by digital transformation and demand for intelligent automation, the region is embedding AI across sectors, reshaping business operations and public services. IDC

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Nvidia supplier SK Hynix warns of demand volatility after quarterly profit soars 158% on AI boom SK Hynix beat Q1 estimates as AI-driven demand for high-bandwidth memory boosted revenue 42% and profit 158% year-over-year. It overtook Samsung in DRAM market share and plans a new $15B+ fab to expand next-gen HBM production. CNBC

TSMC Unveils Advanced A14 Process Amid AI Boom At its North America Technology Symposium, TSMC unveiled its A14 process, promising major gains in AI chip performance and efficiency. Set for 2028 production, A14 strengthens TSMC’s edge amid fierce Intel rivalry and rising geopolitical pressures. EE Times

Sponsor Flip Chip Bonding / C4 technology High pression process of assembly and connection technology (AVT) for contacting unhoused semiconductor chips by means of balls - so-called "bumps". Tresky Automation

Intel Poised to Cut More Than 20% of Staff Intel plans to cut over 20% of its workforce this week under new CEO Lip-Bu Tan, aiming to slash bureaucracy and revive its engineering focus. The move follows past layoffs and asset sales as part of a broader turnaround strategy. Taipei Times

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