August 12, 2026

CPO Test Won't Scale Without Standardization Co-packaged optics can boost AI data-center bandwidth while cutting power and latency, but complex testing, integration, and weak standards slow production. Standardized test architectures could reduce costs, improve interoperability, and speed CPO deployment. Semiconductor Engineering

Sponsor IR Layer Release Technology for 3D Packaging and Logic Scaling Ultra-thin layer transfer from silicon carriers with nanometer precision using an IR laser and inorganic release layers revolutionizes 3D packaging & logic scaling. EV Group

SPIL breaks ground in Yunlin Siliconware Precision Industries has begun building a NT$100 billion chip-packaging plant in Yunlin, targeting CoWoS services from 2028. The facility will expand advanced packaging capacity, create up to 2,200 jobs, and strengthen Taiwan's AI semiconductor supply chain. Taipei Times

A New Optical Ball Grid Array Package Development for Automotive Optical Sensor This study develops a robust optical ball grid array package for automotive image sensors, optimizing materials, design, and processes to mitigate thermal stresses, improve reliability, and meet stringent ADAS qualification requirements. Technical Paper

Sponsor UV DIE Bonding Special Technology Liquid adhesive is cured using ultraviolet (UV) light. In contrast to epoxy, the UV adhesive remains in the liquid state until it is exposed to high-energy UV radiation with UV DIE Bonding technology. Tresky Automation

Samsung Reportedly Eyes High-NA EUV for 1nm around 2030 as TSMC Also Takes a Cautious Approach Samsung targets High-NA EUV for its 1nm process around 2030 as technical and cost hurdles delay wider adoption. Intel already uses it in logic, while TSMC pursues R&D and SK hynix evaluates it for advanced DRAM, including single-patterning. TrendForce

Agentic AI, Multi‑Physics, and Standards Will Redefine Chips Design DAC 2026 highlighted agentic AI's rise in silicon-to-systems engineering, with multi-physics and standards posing key challenges. EDA leaders called for autonomous workflows, more compute and long-running agents to elevate system-level design. EE Times

Sponsor Die-Module Attach (Pastes & Films) Die-Attach Adhesives with low moisture absorption for MSL Level-1 applications for reliability. Outstanding thermal conductivity with low moisture absorption- stress-free bonding. AI Technology, Inc.

Technical Papers A New Optical Ball Grid Array Package Development for Automotive Optical Sensor Automated X-Ray Metrology: Enhancing Quality and Efficiency in Wafer and Panel-Level Applications Alpha Particle Emissions: An Overlooked Risk for Soft Errors in Advanced Packaging Revolutionizing IC Packaging with High-Density RDL Technology EOTPR Fine pitch probing for die-to-die interconnect failure analysis in chiplet devices Die-on-Tab for Compound Semiconductors: Enabling Advanced RF Power Systems Package Assembly Design Kits: The Future of Advanced Package Design MORE TECHNICAL PAPERS

Sponsor Dedicated Tool for Process Development Advanced plating capability at Uyemura Tech Center: Process Development, UBM, pilot production. ENIG, ENEPIG, EPIG/EPAG, RAIG immersion gold; all substrates. On-site analysis. Uyemura

TSMC approves new joint venture with Sony TSMC approved a ¥282 billion investment to launch a Japanese joint venture with Sony Semiconductor Solutions for next-generation smartphone image sensors, targeting volume production in 2029, alongside US$29.44 billion for advanced tech and fabs. Taipei Times

Intel upsizes stock sale to $20B with spending plans still fuzzy Intel has increased its stock offering to $20 billion, seeking funds for corporate needs, potential fab expansion and emerging technologies. Analysts remain divided over whether the capital will strengthen Intel Foundry or support rising internal chip demand. The Register

Sponsor Automotive chips need materials that DO NOT fail We asked semiconductor specialists what defines the future of automotive packaging. Reliability, thermal management, and sustainability topped the list. Free Research Report. Henkel AG & Co.

Nvidia building 1-trillion-parameter Nemotron 4 to rival open AI models, The Information reports Nvidia is developing Nemotron 4 to challenge leading open-source AI models, with its largest version expected to exceed one trillion parameters. The company has not set a release date, but training could finish by late fall. Reuters

AMD Challenges GPU-Centric Architectures as It Takes Aim at Nvidia in Robotics AMD is targeting robotics with its Ryzen AI X100, combining CPU, GPU and NPU on one chip with unified memory. The architecture prioritizes deterministic latency, orchestration and open ecosystems, challenging GPU-centric designs for physical AI applications. EE Times

Sponsor AIT ORMET® TLPS for Proven Reliability AIT ORMET® TLPS is proven for outstanding reliability for High and Ultra High-Density Interconnection and high temperature build-up Layer Interconnection beyond 175°C Ormet® TLPS

Nvidia unveils first open-source AI model since CEO Jensen Huang entered the chat Nvidia is releasing Nemotron 3.5 Lightning, a lightweight open-source AI model that runs on a single GPU, as CEO Jensen Huang backs open models. The move could expand AI adoption, boost GPU demand and challenge proprietary rivals. CNBC

AI Hardware's Next Frontier Is Integration LID World Summit 2026 showed AI's next growth phase will demand more than faster transistors. Leaders called for system-level redesign using advanced memory, 3D stacking, chiplets, photonics, co-packaged optics, and efficient power and thermal management. EE Times

Sponsor Precision BGA Rework Services for High-Reliability Electronics Proven solutions for BGA replacement, reballing, site dressing, and repair that help restore functionality, improve reliability, and extend the life of assemblies. Circuit Technology Center

From Hype To Implementation: Building The Core Pillars For AI In Semiconductors AI adoption in semiconductor manufacturing often stalls because companies lack strong data infrastructure, governance, talent, and operating models. Building these foundations can unlock 15–25% better defect detection, faster cycles, lower wafer costs, and sustainable long-term ROI. Semiconductor Engineering

Sponsor High-Speed, Reliable Plating with PACLINE® PACLINE® delivers high-throughput, precision electroless plating with full automation—ideal for UBM, RDL, and wafer-level packaging in semiconductor production. View Solution. PacTech