Oct 30, 2026 Auto-Generation of Properties: Methodology Insertion AI can speed semiconductor verification by generating formal properties, but weak specifications and faulty assertions pose risks. Experts urge machine-readable requirements, output validation, preserved engineering skills and gradual adoption. Semiconductor Engineering

Sponsor Proven SiPaste® for Ultrafine-Pitch Printing Boost SPI yields with SiPaste® C312HF. Formulated for fine feature printing, it combines best-in-class stencil print transfer efficiency and excellent stencil life. Indium Corporation

ASE raises capex budget to US$11.5bn ASE Technology raised its 2026 capital expenditure budget to US$11.5 billion for the third time, citing surging AI chip packaging demand. The company expects persistent capacity constraints, stronger LEAP revenue and continued growth in advanced packaging services. Taipei Times

Die-on-Tab for Compound Semiconductors: Enabling Advanced RF Power Systems This white paper explains why die-on-tab is critical for GaN and GaAs RF power devices, improving heat dissipation, reliability, and system life. Download now. Technical Paper

Sponsor High Capacity & Power Plasma Systems The BT-1 high capacity plasma systems features 5 shelves & high power plasma up to 5000 watts! Reactive Ion Etching chamber configurations with liquid cooling are also available. Plasma Etch

Intel stock plunges 21% as chipmaker blames PC slowdown for weak guidance Intel shares plunged over 20% after the chipmaker issued a disappointing fourth-quarter forecast, citing weak PC demand and production disruptions. Despite 78% growth in data center and AI revenue, declining PC sales and factory damage threaten near-term performance. CNBC

Chinese markets lose trillions as race for AI supremacy with US takes its toll China's stock market has lost $2.4 trillion since May as AI investment fears, weak consumer demand, shrinking profits and potential US technology restrictions undermine investor confidence, despite Beijing's efforts to strengthen its domestic technology sector. Taipei Times

Sponsor Enabling A Chiplet Supply Chain Chiplet-based architectures are gaining popularity for their smaller die sizes and better yields, but challenges in power management, security, and supply chain complexity remain. Download now. Amkor Technology, Inc.

Technical Papers ■ The Future of Flip Chip Bonding: How R-LAB and R-LTC Enable Next-Generation AI and HPC Packaging ■ Selective Alkaline Wet Etching of Al and AlCu Using a Phosphoric and Nitric Acid Free Formulation ■ Hybrid & Fusion Bonding: from Heterogeneous Integration to 3D Front-End of Line Technologies ■ Why Metal TIM Warpage Simulations Fail—and How to Fix Them ■ Oxide Reduction for Reliable Power Electronics Manufacturing ■ Bond front velocity in lubrication-mediated bonding of flexible substrates ■ How AI Could Cut Semiconductor Package Design Cycles from Months to Days MORE TECHNICAL PAPERS

Sponsor Temporary Bonding Materials Brewer Science offers temporary bonding solutions with high adhesion and high thermal stability (≥ 400˚C) to enable thinning ≤ 50 µm. Brewer Science

Samsung raises spending to 60% after AI chips sell out Samsung Electronics plans to boost capital expenditure by over 60% to US$63.1 billion as AI-driven memory demand surges. However, missed earnings expectations and delayed shareholder payout plans disappointed investors, highlighting competitive pressure from SK Hynix. Taipei Times

Samsung Electronics Posts $80B Operating Profit on AI Memory Demand Samsung Electronics posted record third-quarter revenue and profit as AI demand lifted memory sales and DRAM and NAND prices. Higher chip costs squeezed consumer electronics margins, widening the divide between semiconductor and device businesses. EE Times

Sponsor EZ-FLO High Precision Dispense Tips Each needle is machined from solid stainless steel as opposed to rolled tubing. The resulting smoother internal profile enhances material flow and consistency. Learn more. DL Technology

How AI Redefines Semiconductor Manufacturing, From Materials Up Engineers are advancing specialized ceramics and packaging technologies to meet AI chip demands, improving manufacturing precision, thermal management, signal performance and reliability as semiconductor designs become increasingly complex. EE Times

Rethinking Shift Left in Chip Design Semiconductor Engineering experts from Synopsys, Hiveware, Silvaco, and Axiomise examine the benefits & drawbacks of shifting left in chip design. They discuss how evolving design workflows, verification challenges & changing requirements influence earlier engineering decisions. Semiconductor Engineering

Sponsor Effect of Package Warpage and Composite CT on Failure Modes Researchers analyze board-level reliability of surface mount devices in thermal cycling, identifying failure modes via warpage and strain data. Akrometrix

The Complexity Between the Bits Biological reasoning can strengthen chip verification by revealing context, timing and system interactions. Engineers advocate formal-first design, AI-assisted root-cause analysis and cross-team ownership to ensure complex systems meet requirements. Semiconductor Engineering

Is It Getting Hot In Here? Why Thermal Is No Longer A Signoff Problem Rising chip power density makes thermal management essential, prompting engineers to integrate multi-physics analysis earlier. Combining physics-based simulation, AI automation and scalable modeling helps teams detect risks, optimize designs and strengthen system reliability. Semiconductor Engineering

Sponsor Award Winning Acquisition Mode Dynamic Planar CT Nordson's Dynamic Planar CT™ earned a 2025 EM Innovation Award for its advanced 3D AXI software, delivering faster, ultra-high-resolution defect detection with improved throughput and reduced radiation exposure. Nordson Test & Inspection

Physics-Based Validation: The Foundation Of Trustworthy Agentic EDA Siemens uses physics-validated AI agents to autonomously manage complex 3D-IC design workflows, verifying decisions with signoff-grade EDA tools. The approach cuts engineering effort 95%, accelerates tool configuration 20-fold and expands design exploration. Semiconductor Engineering

Sponsor Void-Free Pressure Curing with Ultra Clean Results Trusted for bond integrity in optical modules and 3D packaging. Achieve void-free curing results in an oxygen-controlled, contamination-free atmosphere. Heller Industries

Scaling Autonomous Root Cause Analysis For Regression Triage AI-native debugging tools such as ChipAgents automate root cause analysis by exploring failure traces, testing hypotheses and ranking explanations. The technology helps engineers pinpoint complex semiconductor bugs and manage large regression failures more efficiently. Semiconductor Engineering