Sally-Ann Henry, Chief Technologist, ACM Research

Engineering the Future of Chiplets: Innovations in Advanced Packaging

In 2026 and beyond, advanced packaging is poised to spearhead semiconductor innovation. Artificial intelligence (AI) and high-bandwidth memory (HBM) workloads continue to push device sizes, interconnect density, and power demands, accelerating the shift from traditional wafer processes to glass substrates and 3D stacking. Quantum computing and its need for specialized semiconductors to support quantum bits for next-generation computing will also be a dominant driver.

Chiplets will remain central, but the industry’s focus is expanding from what we integrate to how and where integration occurs, with wafer-level packaging (WLP) and panel-level packaging (PLP) both shaping the path forward. WLP will continue as the leading method for 3D integration, especially for AI and HBM devices on 300mm wafers with silicon interposers.

Meanwhile, PLP is quickly emerging as the next pivotal step for cost and capacity, with Yole forecasting the PLP market to reach $600 million by 2030. This growth can be attributed to its cost advantages and higher area utilization, simultaneously meeting the technical requirements of both advanced and traditional packaging.

High-end fan-out panel-level packaging (FOPLP) and 2.5D interposer technologies are expected to propel AI, HPC, mobile, and premium consumer applications, with glass panels enabling more dies per substrate and improved economics. However, scaling panel sizes—from 310 × 310mm toward 600 × 600mm—will increase complexity, standardization needs, and capital requirements.

Developing differentiated advanced packaging solutions plays a critical role in meeting pressing challenges across these dynamic areas of innovation and growth. At ACM Research, we remain committed to collaborating closely with customers to develop innovative, differentiated WLP solutions while also enabling PLP’s shift from pilot lines to high-volume manufacturing.