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March 12, 2026
VIEWPOINT 2026: Dr. Dev Gupta, CTO, APSTL llcAdvanced Packaging is now in the Spotlight – the Good News and the Bad News, with recommendations for the way forward
The current boom in AI would not have been possible without the use of Dense Off Chip (i,e. on the Package Substrate / Interposer) Integration (or DOCI) – P using AP to control Package level Parasitics and thus improve Bandwidth / BW density as well as Power consumption. In the last decade or so the Semiconductor industry has followed the theoretical and technology guidelines that were outlined in an Opinion piece at SPN back in 2014 [1]. Components crucial to AI Modules e,g. HBM (DRAM dies stacked using u Pillar Flip Chip & TSVS) are direct application of theories and technologies outlined in that 2014 summary of AP technologies developed and ramped to HVM in the previous 20 yrs since the 1990s. However, the use of DOCI for AI (primarily by new Offshore suppliers of US based Fabless Co.s) has been neither innovative (though accompanied by a deluge of new acronyms – a case of old wine in new bottles), nor cost effective. As an example, on a per GB basis the cost of HBM DDR is 3 to 5x higher than basic LP DDR 5X memory used in Smartphones. This cost differential is mainly due to theoretically shallow designs (very mechanical, as if designed by the all too abundant horde of interfering but unqualified Mechanical Engr.s) and resulting low yields. Consequently, there is now a shortage of HBM memory. Better design of HBM (i.e not just keep increasing the no. of dies in the 3-d Stack or the no of TSVs per layer, as is the case for HBM 4 now under development) that comprehends in depth the theories behind AP, could result in improving the supply of HBM by 25% as well as halve their cost. There is also considerable confusion in the design of Multi Chip Modules of Processors (GPU, CPU, APU / Neural Processors) and in scaling them up fundamentals of Electron Dynamics in materials seems to have been forgotten causing longer Latencies thus degrading computing performance for most Algorithms needed for AI Training. Most distressing however is the fact that even the once "strong in theory" US based IDMs where AP had been pioneered (NOT in US academia or overseas), seem to have forgotten one of the main uses of DOCI – P, i,e. rapid improvement of Fab Yields using DOCI – P as an interim measure when Front End (Transistors) process development is delayed. Failure to apply DoCI – P for rapid Yield Improvement in the Fab (possible to go from 40 to 80% yield within a mere 2 quarters) has caused considerable delay (at least 2 yrs) and consequent turbulence to the last US based IDM in qualifying the leading edge node (1.8 nm GAA) for HVM revenue products. For the benefit of the new non technical management of this IDM, the theory behind Yield Improvement by DOCI – P and past successes have been detailed in a recent technical paper [2]. At the Adv. Packaging sessions in 2025 SEMICON West held in Phoenix AZ [3] it became clear how the Fabless Co.s of the Silicon LESS Silicon Valley have been spending too much for Adv. Packaging provided by their overseas vendors, who are merely tertiary users, not the pioneers. The situation has been further aggravated by US Govt. CHIPS, led by inexperienced poseurs from a once pioneering System Co. that had failed to keep up with Adv. Packaging. Instead of recognizing the enormous contribution of AZ based pioneers of AP (both the technologies and the world first HVM tools and Fabs since the mid 1990s) CHIPS has awarded multi billion $ financial aid to the offshore companies who had been replicating US developed AP technologies (80 % of AP techs used to construct the latest AP Modules today were developed and first put into HVM in AZ starting in the mid 1990s) but till now have failed to develop any robust and cost effective replacements of their own. But it is not yet too late for the powers that be to recognize the contribution of AZ based pioneers of Adv. Packaging and help them reduce the cost of AI drastically e,g. by financing them to bring to market cost effective HBM LC (Low Cost), only one among many innovations in the hopper and re invigorate the completely Robotic manufacturing of AP which too was developed (along with Machine Vision controlled Assembly Robots for both major types of Flip Chip and Organic Substrates invented in AZ that have since become industry standards) and put into HVM in AZ by the mid 1990s. But first the true history of Adv. Packaging must be acknowledged by the Chip Designers (EEs rather than all rounder Physicists) of the Fabless Co.s of the Silicon LESS Silicon Valley. Otherwise, they will keep spending billions more for their outsourced hardware (just for HBM 3E last year they could have saved $15 billion!). The second tier AI hardware Co.s would benefit most from better supply and lower cost of HBM (incl. upcoming HBM 4) and should take note. References : 1. Gupta D., Opinion in Semiconductor Packaging News, Feb 06, 2014 2. Gupta D., paper on “Yield Improvement by DOCI – P“, IEEE Electron Devices Newsletter, Oct 2025 3. SEMICON West 2025, Phoenix, AZ, Oct 7 th Advanced Packaging Sessions. Dr. Dev Gupta, CTO APSTL llc http://www.apstl.com |
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