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Ultra-Thin Wafer Handling
Achieve ≤ 10 µm device thinning with Brewer Science’s BrewerBOND® VersaLayer system: a thermoplastic layer coats device features, while a low-stress adhesive bonds them.
Brewer Science
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| Viewpoint |
March 2, 2026
VIEWPOINT 2026: Sanjeev Aggarwal, CEO, Everspin Technologies
Why Memory Decisions Are Shifting
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Sanjeev Aggarwal, CEO, Everspin Technologies
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As we head into 2026, memory decisions are becoming less about lowest cost per bit and more about how systems actually behave in the real world. Power, reliability, and speed now drive many of those decisions, especially as edge AI, industrial automation, and aerospace applications continue to scale.
We are seeing this clearly with non-volatile memory. In edge systems, for example, the ability to remain powered down until computation is needed, then wake up instantly, changes the entire power equation. In industrial systems, power loss happens. When it does, the system has to come back up immediately with the data intact. If it can't do that, it becomes a problem very quickly, and that’s where standard memory solutions start to fall short.
Aerospace applications bring a different constraint. For applications like low-Earth-orbit satellites or factory automation, memory has to work the first time, every time. There isn't time for long updates or recovery steps, and there’s no room for batteries just to keep data alive. If power drops, the system needs to come back up with the data intact and keep going.
Interface standards are evolving as well. Designers are moving away from wide parallel interfaces, largely because of the area and power overhead they introduce. Serial interfaces make more sense. Octal SPI is already widely used. In some designs, teams look to DDR-style interfaces when bandwidth becomes the priority, but power remains the limiting factor and ultimately drives the decision.
The industry is moving away from embedded solutions that require the use of coherent logic and memory. Advanced packaging that enables integration of chiplets of memory and logic from different CMOS nodes is a cost-effective solution.
Sanjeev Aggarwal, CEO
Everspin Technologies
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Current Characterization of Various Cu RDL Designs In WLP
This study evaluates copper redistribution layer fusing currents in WLP through experiments and simulations, finding that silicon thickness significantly improves heat dissipation and fusing performance.
Amkor Technology
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