Viewpoint - Sally-Ann Henry
February 16, 2023

VIEWPONT 2023: Sally-Ann Henry, Business Development, ACM Research

VIEWPONT 2023: Sally-Ann Henry, Business Development, ACM Research
Sally-Ann Henry, Business Development, ACM Research
Advanced wafer-level packaging (WLP) provides a method to combine and interconnect components before traditional electronic packaging. It allows multiple devices to be merged and packaged on the wafer before dicing, creating a single electronic device in the fab.

According to Allied Market Research, the global WLP market is projected to reach US $23.6 billion by 2030 – growing at a CAGR of 18.8% from 2021 to 2030. The increase in the use of WLP is driven by I/O requirements that require higher interconnect densities to enable faster, more compact electronic devices. This gave rise to the redistribution layer (RDL), which reroutes chip connections via conductive metal traces. These systems’ compact form factor suits space constraints, packing multiple functions into a single structure.

WLP enables stacking chips vertically and/or tiling them horizontally. The resulting 2.5D and 3D ICs utilize fan-out wafer level packaging (FOWLP) and/or through-silicon via (TSV) technologies to connect multiple layers of dense horizontal interconnects, creating more bandwidth with less power consumption.

For customers requiring RDLs, ACM offers unique wet processing technology, including coaters, developers, scrubbers, wet etchers, photoresist strippers, and platers. These tools can incorporate customer-requested features and integrate multiple technologies to enhance performance and improve output with competitive cost of ownership.

Sally-Ann Henry, Business Development
ACM Research
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