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| Viewpoint | ||
February 10, 2023
VIEWPOINT 2023: Dr. Alfred Zinn, President & CTO, Kuprion Inc.
Starting with the 22 nm CMOS node the increased process complexities raised the cost per transistor despite being able to cram more transistors into a given footprint and with sub-10 nm nodes reaching the limits of what is physically possible. The industry started to realize that shifting from CMOS scaling to a packaging focus would allow a continuation of Moore’s law and economic growth for decades to come: continuing miniaturization by cramming more functionality onto a smaller and smaller footprint using heterogeneous integration with a system level focus which Moore too predicted already in his seminal paper in 1965. That has led to the new Heterogeneous Integration Roadmap (HIR) founded by three IEEE sections with the first edition published in 2019 effectively replacing the ITRS and the "old" Moore's law. Electronic packaging is a very complex field placing very different materials (hence the "heterogeneous") in close proximity that has magnified a large number of compatibility issues with the two key aspects being CTE mismatch and heat dissipation. The packages are not only heterogeneous by material, but also by component type, circuit type, node and bonding/interconnect method. Materials are the key drivers to solve heat dissipation and thermal expansion issues as well as I/O contact miniaturization and a variety of processing challenges. The industry is now starting to realize that traditional solders can no longer serve as contact materials due to their relatively low electrical and thermal conductivity, high CTE, proclivity for IMC formation, low melting point, tendency toward creep and potential for wicking and shorts due to whisker growth especially in the case of SAC solder. The fact that it liquifies during reflow limits how small features can be made reliably to avoid shorting. Analyses have shown that we need a copper interconnect material to enable the performance increases desired by many and to fully utilize new miniaturization technologies such as Cu-pillar/bump and to maximize I/O density to exceed 200,000 in current silicon interposers. The key problems to be solved and the desired characteristics of such a material are: • High electrical and thermal conductivity – ideally like copper • No liquidus phase: sintered material – ideally copper • CTE adjustable over a wide range: Si to Cu i.e. 3-17 • Short solder reflow profile (fast, moderate temperature, benign atmosphere) • No creep, robust electromigration, no whisker growth, no IMC • Ideally room temperature storage & shipping • Little to no pressure for high volume production Kuprion Inc. has develop and matured such a material with its ActiveCopper™ system that fulfills all those desired properties and has already been proven to work in numerous spaces. In 2022 interest exploded in a wide variety of bonding applications including but not limited to: 1x6 mm power devices, 10x10 mm large die, direct large heat sink to component attach, 2 inch DBC AlN and SiN to AlSiC base plate attachment, large thermal via formation, large area glass via and TSV fill, high density copper pillar attach, EMI shielding, and true 3D integration and component stacking. ActiveCopper is incredibly versatile, allows for CTE tailoring over a wide range, comes in a wide variety of pastes and inks, and will continue to garner increased interest in 2023. Dr. Alfred Zinn, President & CTO Kuprion Inc. http://www.kuprioninc.com |
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