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January 3, 2023

VIEWPOINT 2023: Joshua Yoo, President, Core Insight, Inc.



VIEWPOINT 2023: Joshua Yoo, President, Core Insight, Inc.
Joshua Yoo, President, Core Insight, Inc.
Future semiconductor device ESD sensitivity will dramatically reduce from 500 volts to 5 volts for advanced package device in some critical processes.

Memory chip such as LPDDR4 was relatively very robust against CDM ESD qualification testing and industry requirement has set by JEDEC at 500 volts. When LPDDR5 launched, this level can't meet due to faster data rate of device from 3.2 GB/s to 32 GB/s. New design target of this device has given to 250 volts about 50% down. Is the mass production environment well prepared to handle this device? This is questionable.

Not only these challenges, but also advanced technology node device such as M1 Pro chip from Apple would have 125 volts CDM robustness due to their technology shrink down to 5 nm and its bandwidth are 200 GB/s data rate. This chip has been used 2.5D advanced package technology.

Advanced Packages such as 2.5D or 3D IC's ESD sensitivity will dramatically reduce down to 30 volts using die stacking and few critical process steps. CDM 250 volts discharge current was 1 – 6 Amps, but CDM 30 volts device discharge limit would be 100 – 250 mA levels. This will decrease when entering regime of extensive heterogeneous integration based on hybrid bonding which leads to tens of thousands of die-to-die interfaces/mm2 up to 1 million die-to-die interfaces/mm2. To avoid an exponential increase in ESD related chip are and power, the robustness target for CDM die-to-die interface needs to drop to < 5 volts.

To prevent damage such an advanced device during manufacturing, maintaining low voltage level on device or wafer should be the first action in production environment. Conventional ionizers have included switching alternative current (AC) technology and this is no longer allowable for such an advanced device process at close proximity application due to induction field can cause of ESD damage.

Core Insight recently released alternative Steady-State DC technology on bar type ionizers and has less than 5 volts offset voltage and eliminated possibility of ESD damage for advanced package processes.

Reference Document:
1. Joshua Yoo, "ESD Risk Analysis using Pulsed AC Ionization Technology", 2018 EOS/ESD Manufacturing Symposium, Munich, Germany
2. Joshua Yoo, "CPM Limitation Study for AC, Pulsed AC and High Frequency AC Ionizers vs. DC based Ionizers", 2019 EOS/ESD Symposium, Riverside, CA, US
3. White Paper 2, "A Case for Lowering Component-level CDM ESD Specifications and Requirements", May 2021, ESD Industry Council

Joshua Yoo, President
Core Insight, Inc.
http://www.coreinsight.co.kr
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