Technical Paper: Optimizing High Power GaN Device Performance With Eutectic Die Attach

Technical Paper

Optimizing High Power GaN Device Performance With Eutectic Die Attach

StratEdge paper details how to reduce chip-to-package junction temperature to improve GaN chip efficiency and reliability. Learn more about specialized packages for GaN devices and perfecting the packaging assembly process.
StratEdge Corporation

Complete this form to download this Technical Paper.

Your Name

Your E-mail

Your Company

Your State, or Country if outside USA

More Technical Papers

■	Plasma Treatment during Fan-out Wafer-Level Packaging Optimizes Performance and Costs
■	Maskless Lithography Addresses Shift Toward 3D Integration
■	Optimizing High Power GaN Device Performance With Eutectic Die Attach
■	Halogen-free Microwave Induced Plasma Decapsulation of System in Package Modules
■	Challenges to Developing Automotive Grade 1/0 FCBGA Package Capability
■	Complete Warpage Control for Wafers and Panels
■	MEMS Packaging for High Volume Products
■	Material Breakthrough for Fan-In and Fan-Out WLPs
■	Package Converter Compliments Chip Obsolescence
■	Automated Eutectic Die Attach

Full Technical Paper List

We search for industry news so you don't need to.

Search

Free Newsletter Subscription
Semiconductor Packaging News is built for professionals who bear the responsibility of looking ahead, imagining the future, and preparing for it.

Insert Your Email Address