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February 26, 2024
VIEWPOINT 2024: Dr. D. Gupta, CTO, APSTL llc
Compared to Traditional Packaging, Adv. Packaging uses 3-d Area Array Flip Chip Interconnect technologies w/ high I/O density (3 to 4 orders of magnitude higher) and low parasitics (1/10 th) which DOUBLES Systems Performance at only 10 – 15% higher cost! What the more recent beneficiaries of Adv. Packaging i,e. the Fabless Co.s (served by their Offshore Foundries & OSATs) and more SERIOUSLY the policymakers for CHIPS in DC (are from the Semiconductor industry) do NOT know is that 90% of various Adv, Packaging technologies in use today worldwide to manufacture the powerful Modules for AI or HPC were all invented and first taken to high volume manufacturing right here in the US (AZ) since the 1990s at 2 leading US based IDMs, NOT at IBM, nor at any offshore Foundries or OSATs, Govt. Research labs (e,g. IMEC) or any University. Only by applying very high level of theoretical and mathematical methods it was possible to accelerate the development of robust processes that went from lab to HVM (50 million units per year) within 3 years. To restore US leadership in Adv. Packaging quickly, CHIPS needs to tap into the proven expertise in AZ not available at Universities like UCLA. APSTL (Scottsdale, AZ) was founded by the inventor of 2/3 rds of all Adv. Packaging technologies in use today, namely various types of Flip Chip Bumps used for 2 and 2.5d Modules and 3d stacking of Dies, Organic Substrates, Robotic Bonding Tools & Lines for them. He also designed and developed the first HVM Fabs and custom Tools for Flip Chip and Substrates that have since been replicated by newcomers Offshore. CHIPS has allocated $3 billion for Adv. Packaging & Manufacturing (NAPMP) which if used judiciously is enough to restore R&D leadership, as well as medium scale world beating manufacturing of all key components of Adv. Packaging. As a Case Study (out of many) the world’s very first Organic Substrates Fab (set up in 1997 – 98) w/ a capacity of 50 million units per year may be cited. Its design and construction was managed by the Founder of APSTL while at Intel. From lab to HVM in a totally new Fab w/ many Custom tools, Metrology & Robotics (that have since become industry standards) took 1 and ½ years to qualify and cost $350 million. Only by the application of very sophisticated (PhD level) methodologies was it possible to accomplish such a feat. Such Fabs have since been replicated Offshore. Thanks to the Bottom Feeding tendencies among Fabless Co.s, these newcomers have been able to capture the bulk of the $15 billion per year business but further progress (e,g. feature size Shrinks) have been stymied by their lack of education and many false turns have been taken. So now CHIPS, if competently guided, has a golden opportunity to reestablish US leadership in AP in less than 3 yrs and retain it (Ref 1). The first phase should constitute of creating a R&D based prototyping and pilot scale mfr. of these AP technologies that can maintain high yields even for small batches. But Benchmarking & R&D for future technologies (materials, equipment, design, process) e,g. for incorporating Photonics in Glass substrates should be funded w/o delay. Preventing further Technology Piracy should be a key goal. Having completed similar Projects in both the US and Japan, APSTL is the best suited Co. in the world to revive AP in the US and looks forward to assisting CHIPS in 2024 and beyond. References: 1. Gupta D., "Chiplets : the Origin story" invited presentation at NIST / CHIPS Workshop on Chiplet Standards, Dec 12, 2023 Dr. D. Gupta, CTO APSTL llc http://www.apstl.com |
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