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| Viewpoint | ||
February 15, 2023
VIEWPOINT 2023: Dr. Dev Gupta, CTO, APSTL
As the space between adjacent dies in 2-d and or 2.5 d has shrunk from several millimeters to barely a millimeter, the ability to reduce Packaging Parasitics (key to Improving Bandwidth and Power Efficiency to Transfer Data between dies) has pretty much saturated. Now the inter die Interconnect Length in a state of the art 2-d / 2.5 d Package depends mostly on the die size NOT Package. Further reduction of Packaging Interconnect Parasitics to improve System performance would now require 3-d stacking of dies. Interconnect (as in Flip Chip) technologies for 3-d with ability to further shrink are already here (Hybrid Copper Bond) and in products but Thermal solutions that do not add to Parasitics are NOT, and that requires aggressive R&D, as well as transition to HVM in both of which the US used to excel. APSTL (Advanced Packaging & Systems Technology Laboratories) with its long track record of pioneering world leading Adv. Packaging technologies that now amount to some $30 billion in annual production worldwide, is at present involved in R&D for several technologies that would (1) solve the thermal problems of embedding hot Processor dies in a 3-d stack w/o adding to the Parasitics, (2) reduce the barrier to entry for 3-d die stacking, making its high performance available to medium even small scale users. This is done by integrating innovative electrical design and new materials technologies. That is our major goal for 2023. The new $52 billion CHIPS program of the US Govt. has earmarked $ 8 billion just for Adv. Packaging related R&D, Pilot Fab and HVM. It is hoped that the CHIPS program will not get distracted by Marketers posing as Technologists but seek out true Experts who have pioneered the development of Adv. Packaging, including even Robotic HVM in the US, which due to Corporate decisions has now migrated offshore. Dr. Dev Gupta, CTO APSTL http://www.apstl.com |
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