September 4, 2013
Transistor Scaling: What is Ahead of Us?
The last years, logic scaling has transitioned from a mostly lithography-reliant transistor shrink, the era of the so-called easy scaling, to a performance booster era where new materials and new device structures have to be introduced at an ever rapid pace. The challenge of advanced CMOS R&D is the huge number of different approaches and options for materials and device architectures.
Making the right choice is not easy. First of all, we need to understand the physics behind these devices. This is a crucial step for bringing these devices into the fab. The more we understand how these future devices work, what the main functioning mechanisms are, the more straightforward the eventual design can be and the easier implementation in a fab environment will be. Second of all, we need to scan all the different materials available and see which one are most beneficial for a given structure and which are not. Device architecture is a third aspect that
needs to be taken into account. Device architectures can not only boost the
device performance, but also can have a huge impact on process integration.
14nm to 10nm: from FinFET to high-mobility FinFETs
We have introduced FinFET in our 14nm technology platform as a performance booster. We're now scaling down to 10nm, adding additional strain engineering. SiGe alloy stressors in the channel boost carrier mobility. But as devices scale towards the 7nm, the channel is getting thinner, leaving not a lot of room for introducing stressors. So what do we need to scale FinFET down beyond 10nm to the 7nm node?
10nm to 7nm: next-generation high-mobility FinFET
As from the 7nm node on, we're looking at using alternative materials for the channel in order to boost the carrier mobility. Materials that have an intrinsically higher mobility such as III-V materials and Germanium can boost the carrier mobility. Today two options are emerging. First of all, the Ge-Ge option where germanium is used both in the p and n channels. This approach would require compressively strained Ge in the p channel and relaxed Ge in the n channel. This is not easy, since there are issues with the gate stack and dopant activation. The second approach is the Ge-InGaAs option, where we use Ge in the p channel and Indium Gallium Arsenide in the n channel. InGaAs offers very high mobility, up to 10 times and higher.
10nm to 7nm: gate-all-around FinFET
The recently introduced FinFET architecture provides a better electrostatic control of the transistor channel. Exploring this idea further, we foresee nanowire transistors where the channel is completely wrapped by the gate. There are still lots of challenges with GAA. We still need to address the source/drain contact issue. The surface roughness needs to be improved and the variability issues need further study.
Beyond 7nm: vertical FinFET
The use of vertical nanowires could provide some interesting advantages. Currently, the investigation of such very small nanowires using high-mobility materials is high on our R&D agenda.
Beyond 7nm: tunnelFET
Next to this, we also explore steep subthreshold devices such as TunnelFETs, since they allow a further reduction of the supply voltage and power consumption. In tunnelFETs, a tunnel barrier is created at the source-channel contract to increase the drive currents. Using III-V materials, the TFET promises to scale the supply voltage beyond 0.5V. TFETs enable steeper subthreshold voltages. These are necessary
requirements for next generation transistors that need to operate at low power
Beyond 5nm: Graphene FET
With the material and device innovations that we are working on in our labs, we have the tools to enable scaling to the 7nm node. For the technology beyond, we are exploring a host of ideas. Some of these, if they prove viable and manufacturable, will cause a small revolution in this industry. I'm convinced that we're on the brink of a paradigm shift. Some of the imminent breakthroughs may well have an impact comparable to the invention of the transistor more than 65 years ago.
An Steegen , Senior Vice President of Process Technology
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