March 7, 2013

2013 Flip Chip and WLP: Recent Developments and Market Forecasts

Flip chip and wafer level packaging continues to expand to a wide range of applications and device types. TechSearch International's new study, 2013 Flip Chip and WLP: Recent Developments and Market Forecasts, provides unparalleled analysis of the underlying developments and trends in the industry based on the company’s 25-year history of studying the market and critical infrastructure issues.

Drivers for flip chip continue to be performance and form factor. While processors and other high-performance devices have been using flip chip in package (FCIP) for many years, FCIP is also expanding in mobile computing, especially smartphones and tablets.  In units, the compound annual growth rate (CAGR) from 2011 to 2016 is almost 26 percent, while in number of wafers the CAGR is only 13.5 percent because much of the growth is for small size die. The industry is experiencing a transition from solder bump to copper pillar, just as it moved from an evaporated bump to a plated process. While the transition to copper pillar is underway, SnAg remains the Pb-free solution of choice. Using current exemptions, some companies continue to ship products with eutectic and high-Pb solder bumps. The report provides details of flip chip applications, bump types, and pitch trends based on extensive interviews and research.

Increased demand for thinner, lighter-weight portable products continues to drive wafer level package (WLP) growth. These packages offer a small footprint and a low-profile solution that enables ultrathin consumer products such as smartphones and tablets. The CAGR for WLPs in units from 2011 to 2017 is almost 13 percent for the six-year period, while the CAGR in wafers is slightly over 14 percent. While many wire bond designs are transitioning to WLP, some FCIP is also converting to WLP. Analog devices account for large shipment numbers in both units and wafers, but shipments of devices with RF functions are also contributing to strong growth. WLPs have historically been used for low-pin-count applications (≤100 I/O). However, many companies plan to use WLPs for higher-pin-count applications with larger die sizes--up to almost 8 mm on a side. In the case of larger die sizes, companies will have to trade off conventional fan-in technology with 0.35mm or finer ball pitch versus moving to fan-out solutions. A number of companies ship products in fan-out WLPs (FO-WLP). Many configurations use a panel process and can be categorized as an embedded die package (EDP) solution. The use of FO-WLPs will increase if cost, reliability, and supply chain targets can be met, but the EDP may ultimately see even stronger growth.

The 175-page report with full references provides forecasts for the flip chip wafer bumping market by product application, device type, FCIP/FCOB split, number of wafers, and number of die. Merchant and captive capacity is included and projections by bump type and wafer size are provided. Geographic changes in the location of bumping supply are analyzed. Forecasts for WLP demand in number of die, wafers and device type are provided. Bumping, wafer level packaging, and contract assembly service providers are highlighted in terms of capability and experience. Contacts for these companies as well as suppliers of laminate substrates and bonding equipment are provided. A complimentary set of PowerPoint slides accompanies the report.

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