David Ovrutsky, Development Manager, Tessera, Inc.

Key Words: Through silicon via (TSV)), wafer-level packaging, wafer-level camera module, alignment accuracy, wafer-level bonding

Wafer stacking is an important technique for the modern semiconductor industry, and aligned wafer bonding is used in several applications:

a. TSV integration

The most common use of this technology is to stack NAND Flash memory in a miniature multi-gigabyte unit used in Micro SD cards. To produce a thinner stack, the industry is moving from wire-bonding integration to the TSV method, in which the silicon chips can be integrated at the wafer level.(Fig.1)[1]

Fig. 1. Wire-bonded interconnection (left) is being replaced by the TSV stacking approach (right) using wafer-level bonding.

b. Wafer-level packaging

Tessera's SHELLCASETM wafer-level packaging solution for CMOS image sensors uses an aligned wafer-level bonding process for simultaneous encapsulation of the entire active surface of the imaging wafer. The optically transparent glass has patterned square features that seal the imaging area of each die, generating the air cavity above the imaging area (Fig. 2).

Fig. 2. The SHELLCASETM wafer-level packaging solution uses the aligned wafer-level bonding process to create the air cavity between the encapsulating glass and the imaging area.

c. Wafer-level camera module

In this application, several wafers with populated refractive optical elements are stacked together, producing a miniature multi-lens optical stack that is assembled on top of the packaged image sensor.

Fig. 3. Lenses are produced in a wafer form and stacked together using wafer-level bonding processes.

The following process flow is typical for most bonding equipment[2]:

1. Wafer preparation. One or both of the wafers are prepared differently depending on the bonding type:

- Adhesive bonding: Thermally cured adhesive is applied to one or both wafers using spray, spin or other technologies

Industry trend

- Intermetallic bonding: One of the substrates is patterned with indium deposited with a thin layer of gold or silver. The second wafer is patterned with a thicker gold or silver layer. The ratio of the metal thicknesses between the two wafers depends on the eutectic / intermetallic compound desired after bonding[3]

- Anoding bonding: Two crystalline substrates, typically glass and silicon, are chemically treated and polished

- Plasma bonding: Both crystalline substrates, typically glass and silicon, are polished (patterned with silicon oxide, if required) and treated with oxygen plasma to generate high surface energy from the OH groups

2. Wafers are aligned using a tool such as an EVG 620 or a BA8. At the end of the aligning process, two wafers are clamped together in such a way that a gap of a few hundred microns is maintained between the two, due to the presence of three metal flags.

3. After clamping, the bonding chuck is dismantled from the aligner and installed into a bonding tool, such as an EVG 540 or an SB6e/8e, with two heated chucks with a web error compensation (WEC) mechanism inside the vacuum chamber. To prevent anodic bonding, the chucks are electrically connected to the power supply.

4. After the vacuum is generated, the top wafer is prefixed with a small pin in the center. The flags separating the two wafers face out from the cavity between the two wafers. Next, the wafers are brought into contact, and the top chuck generates the desired pressure to heat the chucks to the desired temperature.

The equipment cycle is illustrated in Figure 4.

This bonding approach involves several challenges:

1. Increasing the number of steps between alignment and bonding increases the risk of wafer movement. If one wafer moves during the chuck transfer, it can disrupt the position of the second wafer, separating the flags or interfering with the WEC process during bonding.

2. It can be difficult to ensure that bond-warped wafers are aligned precisely. During the alignment process in the aligner tool, the vacuum chucks flatten the wafers. After alignment, when the vacuum is released, the wafers may warp again, changing the wafers' pattern registration relative to each other. Once the top chuck of the bonding tool applies pressure, the wafers flatten out once more, but without any adjustments to the alignment. This problem causes post-bonding misalignment.

3. The bonding cycle is fairly slow, usually requiring up to 30 minutes. This has a significant effect on CAPEX in mass-production.

Fig. 4. Typical bonding cycle between alignment and bonding tools (EMC-3D SE Asia Technical Symposium, Jan. 22-26, 2007).

The manufacturing of wafer-level camera modules requires very precise alignment between the two lens wafers¡ªmuch more precise than in other applications, such as wafer-level packaging or TSV integration.

The following describes an innovative approach for bonding optical wafers with alignment accuracy similar to that achieved by the lithographic approach.

2. Experimental

Our work demonstrates the use of a UV adhesive (3553-UTF-HM epoxy) to bond two optical wafers. An advantage to this approach is that the wafers bond immediately after alignment, while still held in place by the vacuum chuck.

Our equipment setup uses an IQ Aligner. Our bonding process uses a nanoimprint lithography (NIL) setup, which is capable of large-gap alignment (Fig 5).

1. Our setup consists of two chucks. On top is a transparent vacuum chuck with a UV source above it.

Both chucks can move vertically, and the bottom chuck can move horizontally to align the two wafers on the X and Y axes

2. First, a transparent wafer is loaded on the bottom chuck. The wafer surface does not need to be 100% transparent; 50% transparency will be effective as well.

3. The bottom chuck lifts the wafer to the top vacuum chuck.

4. The bottom chuck returns to the load position.

5. The second wafer is coated with a UV adhesive and loaded onto the bottom chuck.

6. The bottom chuck brings the second wafer to a predefined distance from the first wafer, and the two wafers are aligned.

7. After alignment, the second wafer is brought into contact with the first wafer, and the stack is exposed to UV radiation through the top, transparent chuck.

8. Finally the bonded stack is unloaded from the system.

Fig. 5. Process flow using UV-sensitive adhesive as a bonding substance.

The alignment can be observed in real time (Fig. 6).

Since the adhesive is immediately cured by UV radiation after alignment, the wafers' relative registration cannot change.

Fig 6. Relative registration of the alignment marks from the two wafers observed on the IQA aligner in real time.

3. Results

Data from the post-bonding alignment of the 11 bonded wafers are presented in Table 1 below. The alignment was measured on an UltraMet 100. Each stack was measured twice, from where the top wafer faces the UltraMet 100 chuck and where the bottom faces the chuck.

Table 1. Row alignment data for wafer-to-wafer bonding.

Our results are presented in Table 2. Note that these numbers are very close to the lithography spec, since we performed the bonding process on a tool with NIL capabilities.

Table 2. Statistical analysis of the row data.

Source

Alignment accuracy is strongly correlated with optical performance, as shown in Figure 7, which depicts sample MTF plots of poorly and properly aligned optics. In the properly aligned examples, the MTF curves of the different field-of-view angles overlap sufficiently, providing higher MTF values on a sufficiently wide FFL window. In the poorly aligned optics, the curves are split.

Fig 7. The MTF plot of properly (left) and poorly (right) aligned optics.

4. References

[1] "Market trend for 3D stacking", Yole Developpement, EMC 3D, June 2007, p. 5.

[2] EMC-3D SE Asia Technical Symposium, Jan. 22-26, 2007.

[3] "Low Temperature Eutectic Bonding

For "In-Plane Type Micro Thermoelectric Cooler", Da-Jeng Yao, Gang Chen, and Chang-Jin "CJ" Kim, Proceedings of 2001 ASME International Mechanical Engineering Congress and Exposition, November 11-16, 2001, New York, NY.