IMEC has used its SiGe-based MEMS platform to build micro-mirror arrays that meet the stringent requirements of today’s high-end industrial micro-mirror applications. In a broader perspective, the SiGe MEMS-last approach offers a generic technology for the monolithic integration of high-quality miniaturized devices on top of standard CMOS circuitry. In this particular case, it ensures the mirror’s mechanical reliability, device flatness and compatibility with foundry CMOS.

Today’s evolution of micro-electromechanical (MEMS) devices demands a generic technology that enables the creation of a whole range of cheap, highly integrated miniature systems with improved performance over current options. In answer to this demand, IMEC has earlier proposed a SiGe-based platform, where poly-SiGe is used as a structural material for the realization of surface micromachined SiGe devices that are integrated with CMOS in a MEMS-last approach.

MEMS structures are thus fabricated on top of the CMOS wafer after completion of the CMOS processing, which enables an efficient use of the Si area. The choice of SiGe is quite obvious: it offers very interesting mechanical, electrical, optical and thermal properties for MEMS applications.

Since SiGe layers can be processed in state-of-the-art CMOS tools, this technology enables the development of very small MEMS structures. Poly-SiGe can be deposited on the CMOS wafer using e.g. plasma enhanced chemical vapor deposition (PECVD). SiGe surface micromachined structures are then defined by i-line or deep-ultraviolet (DUV) lithography, (deep) reactive ion etching and removal of the sacrificial PECVD-deposited Si-oxide layer by HF-etching.

IMEC micro-mirror: Cross-section of the integrated micro-mirror array, showing the mirrors on top of the 6 layers of interconnect

This process results in high-quality poly-SiGe material deposited at temperatures (typically 450°C) that are compatible with CMOS circuitry. When using hydrogenated microcrystalline SiGe (µc-SiGe:H), the structural layer can be deposited at even lower temperatures (300-400°C). Here, the use of a high hydrogen flow together with a large plasma power, encourages the crystallization of the SiGe layer on the CMOS wafer.

The processing of SiGe does not pose any contamination problems for the CMOS process environment. A number of successful applications, including micro-bolometers, thermopile arrays for energy harvesting, accelerometers and gyroscopes, could already demonstrate the versatility of this technology. The approach not only aims at meeting performance specifications, but also at fulfilling reliability requirements.

A similar technology can moreover be used to package MEMS devices with a surface micromachined thin film shell. It is therefore on the path to replace wafer-bonding techniques in MEMS packaging applications and to open markets for smaller, less expensive MEMS packages.

This SiGe above-IC process has now enabled IMEC to fabricate highly reliable micro-mirror arrays. Such devices are a very good alternative to the traditionally Al-based micro-mirrors that often give rise to reliability problems (i.e., the hinge memory effect). Replacing Al by Si could also solve the problem, but integrating Si mirrors with a CMOS driving circuitry can only be accomplished through wafer or die bonding techniques.

Conversely, the use of poly-SiGe offers much better integration possibilities. It can meet all flatness, uniformity and reliability specifications for future demanding high-end industrial micro-mirror applications such as video projection or lithography mask writers.

In more detail, the 8µm x 8µm mirrors were fabricated on top of high-voltage 0.18µm CMOS 200mm wafers with 6 interconnect levels coming from NXP. To prevent attack of the CMOS during the vapor HF (VHF) or wet HF release, it is protected with a SiC layer. This layer is perforated with more than 50 million W-vias per device to connect the mirrors to the underlying driving circuitry.

To ensure perfectly flat mirrors and a well controlled actuation gap, the electrodes are planarized by oxide deposition and chemical mechanical polishing (CMP). The thickness of the actuation gap is therefore only defined by the subsequent sacrificial oxide deposition. A 300nm µc-SiGe:H film is used as a structural layer and to fill the 1µm posts in the sacrificial layer.

The small SiGe grains (50 – 100nm) ensure uniform and reproducible mechanical properties of the 350nm wide hinges. The structural layer consists of a 250nm base layer and 50nm stress compensating top layer to obtain a strain gradient below 4.10^-4 ìm^-1. Optionally a stress-free phase step layer of SiGe is deposited, and a phase step is created in each mirror by removing it selectively from half the mirror area through a timed etch.

The RMS roughness was reduced from 5nm as-deposited to around 0.3nm by an optimized CMP process. This CMP process results in a reflectivity of 45%, which can be increased to above 80% by coating the SiGe mirror with a thin 30nm Al layer. The process is finalized by adding Al bondpads and releasing the mirrors either in buffered HF followed by critical point drying (CPD), or in VHF (in case of Al coating).

Applying this process resulted in a 10cm² 11 megapixel micro-mirror array, a world’s first both in terms of pixel density and reliability. The pixel density is almost double that of comparable state-of-the-art micro-mirrors. The mirrors show no creep and have a mechanical lifetime above 2.5x10¹² cycles. They have stable average cupping below 7nm. Each mirror can be individually addressed by an analog voltage to enable accurate tilt angle modulation.

These highly stable and extremely reliable SiGe-based micro-mirror arrays are a nice demonstration of the potential of the SiGe above-IC MEMS-last approach. This approach offers a generic technology in which different MEMS devices can be processed together on top of standard CMOS. In a broader context, the activities fit in IMEC’s CMORE initiative, which offers cost-effective solutions for continued system scaling, not by shrinking CMOS, but by focusing on monolithic co-integration of heterogeneous technologies.