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| Viewpoint | ||
January 20, 2020
VIEWPOINT 2020: Keith Felton, Manager, Product Marketing, Mentor
We will have to innovate in other ways. One path is to integrate, on package, using smaller high-yield chip(let)s. Even with known good chips still leaves open questions. Primary 'what is the best way to combine these chip(let)s into a working system'. There are lots of established methods: 2.5D integration on a silicon interposer is one popular approach. Then there are simpler connections from die to die through super thin, and often very small, bridge-like interposers that do not require TSVs. Then of course there is die-to-die connections through package RDL in the form of wafer-level fan-out processes. Going to full 3D-IC opens up even more options. Ultimately the choice of how to best integrate will depend on the design requirements. The right approach is to digitally prototype so early predictive analysis can be used to evaluate viability. Mentor's High Density Advanced Packaging (HDAP) platform provides a true 3D virtual model that can be analyzed not only for routability, signal and power integrity but also for structural performance such as thermal stability and thermally induced stress. Keith Felton, Manager, Product Marketing, High Density Advanced IC Packaging Mentor http://www.mentor.com |
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