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Viewpoint Index

January 19, 2017

VIEWPOINT 2017: David Butler, EVP and General Manager, SPTS Technologies
VIEWPOINT 2017: David Butler, EVP and General Manager, SPTS Technologies
David Butler, EVP and General Manager, SPTS Technologies
FOWLP and other Wafer-level Packaging. "FOWLP first appeared in the late noughties and was used for PMIC and RF devices with modest line & space dimensions. It was also in relatively low volume production. 2016 was the year when fan-out wafer level packaging went mainstream when teardowns of the iPhone7 confirmed that the microprocessor incorporated TSMCs InFO package.

With the successful transition to high performance silicon, we expect to see more AP providers taking advantage of FOWLP through 2017. SPTS is well positioned to benefit from this move; our Sigma PVD system provides the RDL and UBM layers for the majority of FOWLP parts on the market today.

It is not just FOWLP that will grow; there is a general move in the industry toward proliferating wafer level packaging of all types - fan-in, flip chip. For example, the iPhone7 had around 38 WLPs, up from 29 in the 6S.

That 30% increase is possible because the cost of WLP has reduced to the point where it makes sense for the OSATS to move previously wire-bonded packages to wafer level, and get the advantages of better performance in much smaller form factors. In 2017, we expect to see a rise in demand for WLP equipment and not just on 300mm wafer formats; older technologies on 200mm will also transition to WLP.

Plasma dicing is another packaging technology that will see more adoption in 2017. In 2016, we launched and shipped our first Mosaic fxP system for dicing 300mm wafers on frames. Manufacturers of tiny die such as RFIDs can put far more die on a wafer, because unlike saws, plasma dicing does not cause micro-fractures in silicon so the dicing lanes can be narrower.

Also for damage reasons, IDMs making very thin die like plasma dicing because dies are >2 times stronger post singulation, compared to saw or laser. At the recent Be-Flexible Forum at Fraunhofer EMFT, many potential applications were highlighted where small, thin die can be combined with printed, flexible electronic structures. One of the speakers claimed that plasma dicing was a must to ensure the standard of chip quality was available to make this happen.

Outside of packaging, we see positive signs in all our markets. In power semiconductors, we'll see more power production on 300mm Si, as well as on new substrate materials such as SiC and GaN. Power semiconductors are strategically important to the global economy, being central to the efficiency of renewable energy farms, industrial motors, automotives and domestic appliances.

In MEMS, a new range of actuators based on the piezoelectric effect are appearing. First for microphones and fingerprint sensors, they use piezoelectric materials such as AlN and ScAlN to generate a signal as the layers are strained by an external force (eg a sound wave, or an ultrasonic reflection). PiezoMEMS consume very little power so are attractive for wearables, as well as being highly durable and largely impervious to moisture or dust.

As leaders in piezo processing from our RF activities, we are well placed to serve this market for deposition and etching of these layers. Finally, in RF, this market is driven by our insatiable appetite for bandwidth. A modern worldphone may need to serve as many as 75 different RF bands, which all need to be read without call overlap, and amplified with GaAs PA's.

The move to 5G after 2020 will produce another wave of RF complexity. Increasing wafer sizes, and new piezoelectric materials to deposit and etch will keep us very occupied."

David Butler, EVP and General Manager
SPTS Technologies