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Viewpoint Index

January 14, 2016

VIEWPOINT 2016: David Butler, VP Product Management & Marketing, SPTS Tech
VIEWPOINT 2016: David Butler, VP Product Management & Marketing, SPTS Tech
David Butler, VP of Product Management and Marketing, SPTS Technologies
We think 2016 will be a signal year in advanced packaging. A number of projects we have been working on will see significant adoption and growth next year. In 2015, SKHynix, Micron and Samsung took 3D memory die stacking using TSV into production, and AMD was the first chip maker to use the memory cube in their Radeon GPU 2.5D package. That milestone proved the value of the technology and we expect to see a number of other chip makers launch similarly enabled products in 2016.

Staying with the theme of TSV, we also expect to see a resurgence in 200mm lines building via-last TSV's for low I/O die such as PMIC's and MEMS devices, replacing wire-bonds to shrink package area.

Another key area of continuing focus for us in 2016 is Fan Out Wafer Level Packaging. In September 2015, Yole Développement revised its FOWLP forecast, projecting a CAGR of 54% with packaging revenues rising to $2.4B by 2020. We expect FOWLP to become the leading low cost, high density packaging format, and is a large driver of demand for our Sigma® fxP PVD system which is used to deposit RDL and under bump metals on die embedded inside epoxy mold compound.

FOWLP has been around for a few years as a niche technology but with TSMC and its InFO technology entering the market, the platform will begin to take share of larger, high performance die. We expect to see a number of new FOWLP announcements in the coming months. Our Sigma® fxP is the leading PVD system in this market, carrying novel degas and preclean technology to deal with the challenges of high levels of contamination from the mold compound and potentially particle-shedding organic dielectrics.

Another new area set to drive growth is plasma dicing, which uses our well-established silicon etch technology to singulate die on frame-supported wafers. Plasma dicing has significant benefits in two main areas; for tiny die (PMICs, RFID) where a reduction in dicing lanes can deliver up to 80% more die per wafer and for thinner packages (eg memory) where it enables much thinner silicon because of the non-damaging nature of a chemically driven etch singulation. We expect to see a number of device makers adopt plasma dicing in 2016, using our Mosaic™ fxP etch system.

David Butler, VP of Product Management and Marketing
SPTS Technologies