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January 29, 2015

Dr. Dev Gupta, CTO, APSTL
Dr. Dev Gupta, CTO, APSTL
Dr. Dev Gupta, CTO, APSTL
The wait for 3-d stacked Processor & Memory to appear in products is beginning to look more and more like "Waiting for Godot", Beckett's famous play!

Back in the early 1990s it took only 3 years for a leading US based IDM to develop the now common electroplated solder bump flip chip technology and implement them into ASICs This lower cost version including Cu pedestals has now completely replaced IBM's original evaporated C-4 bump technology. This electroplated bump technology also included in house development of bump plating tools employing CFD modeling as well as robotic Bonders using advanced vision algorithms that reduced cost and have now become industry standards.

The development of Sn-capped 50 um pitch plated micro - bumps, complete with rapid thermo-compression flip chip bonding techniques and robots for same was even faster and saw first application in Gallium Arsenide Power Amplifiers in Motorola Flip phones way back in 1997 and radically expanded the prospects of the compound semiconductor industry.

At Intel the development of high yield manufacture of organic substrates for flip chipped processors took only 2 years and went into volume production by '98. This substrate technology has now diffused down to LCMRs and is used even in Smart Phones, turning it into a $10 billion a year industry with a margin better than most semiconductor foundries!

Why then is it taking so long to bring to market 3d stacks using TSVs or to even get wider adoption for the simpler 2.5 d Interposer technology?

While it is only too easy to blame over eager bloggers keen on advertising revenue who have been hyping the technology while not even comprehending its technical challenges, the clue lies elsewhere.

The key factor in the delay to implement TSV technology has been the absence of US based IDMs with demonstrated track record in Adv. Packaging from the TSV scene. Even the system company that around 2007 first kicked off the deluge of technical papers on 3-d die stacking with TSVs, has recently divested of most semiconductor production.

For IDMs with no prior track record in pioneering Adv. Packaging, die stacking with TSVs have been a tough nut to crack, as no commercial product has appeared in the 3 years since the first publication of DRAM stacked in the Wide I/O format. Most IDMs have abandoned in - house Adv. Packaging activities and transferred technologies e,g. Flip Chip & WLPs developed by them to the OSATs.

Through these OSATS the Fabless companies have gained access to Adv. Packaging technologies developed at IDMs, but they do not invest in technology development, leaving the Foundries & OSATs to bear the brunt.

However as yet the OSATs lack the theoretical depth and comprehensive capabilities of leading IDMs to develop on their own a brand new technology as complex as die stacking with TSVs. They have had to depend on new-fangled / aggressive Market Research firms and state funded Research Laboratories located in nations with no real stake in semiconductor production. Comprehensive risk assessment and efficient theory - driven development has suffered.

It took the flip Chip industry nearly 4 years to get a handle on the chip package interaction (CPI), a problem brought about by RoHS dictated recent change to more rigid interconnects. Interactions in a die stack are just as complex. The technical challenges of stress and temperature effects on transistor performance and non - uniformities of same in those buried deep in the stack had been predicted by modeling but are being recognized only recently. Equally important are yield issues that are magnified in multiple die stacking.

The challenge in process development is not just in solving every problem with the baseline but finding intelligent / theoretically sound workarounds / alternatives. Except for one notable exception (replace the original Cu filled TSVs by shorter W filled TSVs, the damage prone original flow of parallel wafer thinning and then debond / bond by a bond / thin sequence) this is still absent in the common approach to TSV based die stacking with the consequence of still immature process and high yield losses. Many tool makers who had plunged into this new technology and tried to cater to the original process flow have suffered.

APSTL had played a key role in the development of now standard Flip Chip processes. We apply mathematical modeling & simulation not just for package design but also for process development. Before plunging in we do comprehensive risk analyses for the whole process flow not just individual steps.

We see a lot of promise in organic substrates for package level integration at the 2.5 - d level much the same way they had replaced expensive Si based substrates in MCMs some 20 years ago and are applying advanced techniques to develop HVM for 2 um L/S. APSTL is available to provide comprehensive Program Management to OSATS interested in gaining industry leadership in die stacking.

APSTL has also developed unique and elegant packaging alternatives (both 3-d and 2-d) that do not require TSVs to deliver the bandwidth and power efficiency of 3-d die stacks with all their attendant issues. We have proven our "Magic Chip" technology in a PoP configuration for Smart Phones and deliver power efficiency that merely increasing the number of package vertical I/O (as some are trying) w/o addressing the parasitics issue can never do.
Dr. Dev Gupta, CTO