We search for industry news, so you don't need to.
News | Search | Subscribe
Viewpoint Index

February 6, 2014

Dr. Dev Gupta, CTO, APSTL llc

Dr.  Dev Gupta, CTO, APSTL llc
Dr. Dev Gupta, CTO, APSTL llc
Driven by the need to transfer data between the processor and fast memory chips in a Smart Phone with minimum delay, then fit these devices within the restricted real estate while keeping costs down, the industry has been packaging Application Processor and DRAM chips for Smart Phones and most Tablets in a stacked Package on Package (PoP) configuration.

Confident predictions being made a couple of years ago that the PoP package in Smart Phones and Tablets will be replaced by 2.5d modules or 3d stack of chips have not yet materialized. Even for their upcoming 20 nm 64 - bit A8 processor, Apple will stay with the PoP. It has also been reported recently that even the sole Fabless user of 2.5 d modules so far might be reverting back to single chip solutions as the yields at their Foundry improve.

All is not well however with the basic PoP package. When it comes to electrical characteristics (parasitics) it certainly suffers in comparison to a 3-d stack of chips interconnected by expensive but short & numerous TSV based interconnections.

As communication between the Application Processor and latest generation of DRAM (DDR 3 then 4) goes beyond 800 MHz, the digital waveform in the data stream gets distorted due to parasitics of the PoP package, putting an ultimate limit to the bandwidth (and the speed at which the displays can be refreshed for fast games etc.) even when the data width is increased from 32 to 64 bit. More precious battery power is wasted in the package as well.

While several Package development teams have focused only on increasing the number of interconnects in a PoP package to mimic the interconnect density of TSV stacks, APSTL has been working on a technology to reproduce in a PoP package the superior electrical characteristics of TSVs as well. This is done by inserting additional circuitry between the two levels of a PoP package during the package assembly operation so as to virtually reduce the parasitics in a PoP package and bring them in line with that of the technologically disruptive & far more expensive 3-d TSV technology.

The additional circuitry are contained in chips of our design called "Magic Chips". Output waveforms look like those out of TSVs and power lost in packages is reduced by 70 %. Similar benefits are expected for high performance modules now limited by bandwidth.

We expect widespread adoption of our technology among Smart Phone suppliers, especially by chip companies who are trying to break into this fast growing market worth $ 20 billion a year and need to add superior features.

Dr. Dev Gupta, CTO