January 9, 2014
Joseph Sawicki, Vice President & General Manager, Mentor Graphics Corp.
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Joseph Sawicki, Vice President & General Manager, Mentor Graphics Corporation
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"In the area of 3D-IC packaging, although we continued to see a
handful of interesting design releases, and even more customer evaluations,
this past year, it seems like companies are still trying to determine which
products will benefit the most from pursuing 2.5D-IC/3D-IC configurations. Cost
is the major stumbling block at this point, not technical issues. Memory on
memory, image sensor on logic, MEMs on logic, and memory on SoC/CPU/GPU/FPGA
still look like the early contenders.
"Mentor has physical design (Olympus-SoC(TM)) and physical
verification (CalibreŽ) tools that are ready today to handle 2.5D designs with
silicon interposers, and full 3D-IC design using through silicon vias (TSVs).
This includes generating I/O pin-outs for multi-die configurations, routing on
backside metal and silicon interposers, physical alignment checking between
dies and LVS connectivity checking across external interconnects.
We are
working with the major foundries to refine the models for TSVs and these are
already integrated into our extraction tools. Also, our products are a core
component of the 2.5D and 3D reference flows announced by various foundries
including TSMC.
"In the area of test, our Tessent silicon test suite is 3D-IC
ready with the capability to route test patterns to multiple stacked dies using
standard test control protocols. Designers benefit from the fact that they can
use the same patterns created for individual die to test the assembled stacked
die package."
Joseph Sawicki, Vice President & General Manager
Mentor Graphics Corporation
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