June 21, 2012
3D-IC Progress on Display at SEMICON West 2012
Given their potential
for smaller form factors, increased performance, and reduced cost and power
consumption, 3D-IC technologies are now enabling the next generation of
advanced semiconductor packaging. Already, 2.5D technology using silicon interposers to provide wide IO bandwidth
and denser packaging have been introduced, but multiple manufacturing and
collaboration barriers remain to widespread commercialization.
|Denny McGuirk, President and CEO, SEMI|
While 3D integration using through-silicon
vias (TSVs) promise a fundamental shift for current multi-chip integration and
packaging approaches, cost-effective, high-volume manufacturing will be
difficult to achieve without standardized equipment, materials, and processes.
the technical hurdles of implementing complex, new technology in a cost
effective way, 3D-IC technology presents unprecedented collaboration challenges
among IDMs, foundries and OSATS, between diverse chip companies, and throughout
a global supply chain.
and techniques for manufacturing 3D-IC products are emerging; which of these
paths will prove most effective for various implementations has yet to be
determined. Heterogeneous integration
that puts memory, logic processors, and other devices all on one substrate, in
a small form factor, is the long-term goal.
SEMICON West 2012
will feature a number of speakers, programs and exhibitors who will present
diverse perspectives on 3D-IC implementation strategies. On Wednesday, July 11,
the session entitled, "2.5 & 3D Packaging Landscape for 2015 and Beyond" will
examine what the market and supply chain will need to look like to drive true
volume production and adoption of recent advancements in 2.5D (interposer) and
3D packaging. Experts from Altera, Fujitsu Integrated Microtechnology, Georgia
Institute of Technology, and HiSilicon Technologies will be among the
speakers. John Lau, ITRI, and Bill Bottoms,
3MTS, will moderate the panel discussion.
|The market for packaging materials are estimated to grow from $23.4 billion in 2011 to $23.9 billion in 2012, according to the Global Semiconductor Packaging Materials Outlook (SEMI/Techsearch International), Packaging materials as a percentage of total semiconductor revenues will also increase, as chipscale packaging (CSP), wafer-level packaging (WLP), other system-in-package (SiP) type technologies, and stacked-die and other 3-D packaging form factors, become more widespread.|
To achieve the
benefits of 3D integration, an unprecedented amount of industry collaboration
will be required. To facilitate that development, 3D-IC Standards meetings will
be held on Tuesday, July 10 to discuss current and future opportunities for
industry-wide standards. Standards task
force meetings will be held on Thin Wafer Handling, Bonded Wafer Stacks, and
Inspection and Metrology. These activities
are just a portion of what is currently a global, industry-wide effort. Over
125 technologists from industry, research institutes, and academia around the
world have already joined the SEMI 3DS-IC Standards Committee and are at work
on these critical standards.
|Approximately 30,000 microelectronics professionals will attend SEMICON West from July 10-12, 2012 in San Francisco. Leading packaging equipment and materials companies will be participating in the exhibition and packaging and technology solutions will be featured in free TechXPOT sessions on the show floor.|
The International Technology
Roadmap for Semiconductors (ITRS) will also hold their annual public meetings
at SEMICON West. On Thursday, July 12,
ITRS Back End of Line Technologies working groups present the challenges for
future interconnects, Through Silicon Vias (TSVs), the latest roadmaps for
semiconductor assembly, and systems packaging applications.
addition to 3D-IC and advanced packaging programs, on Tuesday, July 10, a free
session entitled "Contemporary Packaging: Achieving Cost Advantage through
Innovation" will delve into the growing complexity, growth and new cost-down
solutions in established technologies, particularly in the analog, power and
automotive spaces. The session will
focus on the optimization of technologies such as cu wire bond, flip chip,
large matrix format and advanced leadframe packages and features speakers from
ASM Pacific Technology, Kulicke & Soffa, Texas Instruments and
For more information on SEMICON West 2012,
please visit: www.semiconwest.org. To
register, click here: http://www.semiconwest.org/Participate/RegisterNow.
, President and CEO