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February 2, 2012

Lessons Learned from 3D DRAM-on-Logic Chip Development

Lessons Learned from 3D DRAM-on-Logic Chip Development
Eric Beyne, PhD, Director, Advanced Packaging & Interconnect Research, IMEC
Three-dimensional (3D) integration is considered a very promising technology for integrated circuit design. It provides numerous opportunities to designers looking for more cost-effective system chip solutions.

It allows further decreasing the form factor of today's systems and eases the interconnect performance limitation. And it makes it possible to interconnect multiple stacked dies, made in different process technologies and originating from different fabs, and this with a >16x higher I/O density than in today's packaging solutions.

The cornerstones of this technology are through-Si vias (TSVs) and microbumps, for which process solutions, reliability and design rules are now becoming available.

But the proof of the pudding is in the eating. Therefore, based on their experience with 3D integration, imec and its partners have designed and fabricated a heterogeneous DRAM-on-logic chip and learned important lessons for future 3D integration projects.

The chip itself consists of imec's proprietary logic CMOS IC on top of which a commercial DRAM is stacked using TSVs and microbumps. Heaters were integrated to test the impact of hotspots on DRAM refresh times. And, the chip contains test structures for monitoring thermo-mechanical stress in a 3D stack, electrostatic discharge (ESD) hazards, electrical characteristics of TSVs and micro-bumps, fault models for TSVs, etc.

What have we learned from building this test vehicle?

Lessons Learned from 3D DRAM-on-Logic Chip Development
Logic IC stacked on a DRAM IC, connected using TSVs and microbumps.
First, from a technological point of view, we learned that a minimum die thickness of 50Ám is required to deal with local hot spots on the logic die. These hot spots are generated by local power dissipation and cause local temperature increases in the memory die. This in turn may cause a reduction in retention time of the DRAM device.

However, our 3D-stacked demonstrator has proven that the DRAM may not be thermally isolated from the logic die since the DRAM die also acts as an effective heat spreader for the logic die. As such the intensity of the hot spot is reduced and thereby the temperature rise in the DRAM device is strongly limited.

Secondly, the results of the various experiments allowed us to calibrate our thermal models which are implemented in 3D electronic design automation (EDA) tools. Besides, we have introduced more than 40 new, dedicated design rules and models for 3D technology, going from basic electrical design rules to specific design-for-manufacturability rules.

Thirdly, we have achieved this milestone in collaboration with our 3D integration partners including memory suppliers, IC manufacturers and OSAT. And we have involved all supply chain partners from the beginning. Therefore, we learned to make clear agreements on all types of parameters, and it incited us to discuss ownership, liabilities and value distribution of DRAM-on-logic.

And finally, we have learned the importance of identifying a clear convincing target application. This allowed us to focus our resources and convince our supply chain partners to support the TSV development. Together with EDA and fabless partner companies, we developed a tool -- our pathfinding flow -- that allowed us to build the case for DRAM-on-logic. With this tool, we also help our partners in evaluating the cost/benefits of DRAM-on-logic for their own designs.

With the pathfinding flow, our partners validate product ideas for 3D, in the early phases of system design, before any large investments are needed. In addition, this rapid design flow contains a model for assessing the cost of 3D integration. So we have not only used this model as a tool for looking at costs and benefits of various designs, but also to drive down the cost of 3D technology.

We are convinced that the experience gained with designing and fabricating this DRAM-on-logic chip will help us to design next-generation 3D-stacked ICs, for application in low-power mobile devices. In addition, it promises to be a likely platform for sensor integration.

It will enable a SoC-like integration of sensors, with analog and digital components, and will allow a radical reduction of form factor. Based on our experience, we believe that for each sensor application, a clear product roadmap must be identified. A roadmap that the supply chain can use to focus the process, integration and design R&D.

Note: This work was executed in collaboration with imec's key partners in its core CMOS programs: Globalfoundries, INTEL, Micron, Panasonic, Samsung, TSMC, Fujitsu, Sony, Amkor and Qualcomm, Xilinx, Altera and Nvidia.



Eric Beyne , PhD, Director, Advanced Packaging & Interconnect Research
imec